公开(公告)号：US20060189083A1

公开(公告)日：2006-08-24

申请号：US11279659

申请日：2006-04-13

申请人： Katherine Saenger ,  Rajarao Jammy ,  Vijay Narayanan

发明人： Katherine Saenger ,  Rajarao Jammy ,  Vijay Narayanan

IPC分类号： H01L21/8234 ,  H01L23/58

CPC分类号： H01L21/31111 ,  H01L21/28194 ,  H01L21/31105 ,  H01L21/31122 ,  H01L29/517

摘要： An ultrathin high-k gate dielectric made for use in a field-effect transistor is provided. The gate dialectric is made by depositing a high-k gate dielectric material on a substrate and forming an ultrathin high-k dielectric by performing a thinning process on the high-k gate dielectric material. The process used to thin the high-k dielectric material can include at least one of any number of processes including wet etching, dry etching (including gas cluster ion beam (GCIB) processing), and hybrid damage/wet etching.

摘要翻译： 提供了一种用于场效晶体管的超薄高k栅极电介质。 栅极方言是通过在衬底上沉积高k栅极电介质材料并通过对高k栅极电介质材料进行稀化处理而形成超薄高k电介质而制成的。 用于稀薄高k介电材料的方法可以包括湿法蚀刻，干法蚀刻（包括气体簇离子束（GCIB）处理）和混合损伤/湿式蚀刻的任何数量的工艺中的至少一种。

公开(公告)号：US20050127417A1

公开(公告)日：2005-06-16

申请号：US10730892

申请日：2003-12-10

申请人： Katherine Saenger ,  Rajarao Jammy ,  Vijay Narayanan

发明人： Katherine Saenger ,  Rajarao Jammy ,  Vijay Narayanan

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L21/314 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/94

CPC分类号： H01L21/31111 ,  H01L21/28194 ,  H01L21/31105 ,  H01L21/31122 ,  H01L29/517

摘要： A method for making an ultrathin high-k gate dielectric for use in a field effect transistor is provided. The method involves depositing a high-k gate dielectric material on a substrate and forming an ultrathin high-k dielectric by performing a thinning process on the high-k gate dielectric material. The process used to thin the high-k dielectric material can include at least one of any number of processes including wet etching, dry etching (including gas cluster ion beam (GCIB) processing), and hybrid damage/wet etching. In addition to the above, the present invention relates to an ultrathin high-k gate dielectric made for use in a field-effect transistor made by the above method.

摘要翻译： 提供一种用于制造用于场效应晶体管的超薄高k栅极电介质的方法。 该方法包括在衬底上沉积高k栅极电介质材料，并通过对高k栅极电介质材料进行稀化处理来形成超薄高介电常数。 用于稀薄高k介电材料的方法可以包括湿法蚀刻，干法蚀刻（包括气体簇离子束（GCIB）处理）和混合损伤/湿式蚀刻的任何数量的工艺中的至少一种。 除了上述之外，本发明涉及一种用于通过上述方法制造的场效应晶体管的超薄高k栅极电介质。

公开(公告)号：US20060166474A1

公开(公告)日：2006-07-27

申请号：US11050790

申请日：2005-01-27

申请人： Philippe Vereecken ,  Veeraraghavan Basker ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Martin Frank ,  Rajarao Jammy ,  Vamsi Paruchuri ,  Katherine Saenger ,  Xiaoyan Shao

发明人： Philippe Vereecken ,  Veeraraghavan Basker ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Martin Frank ,  Rajarao Jammy ,  Vamsi Paruchuri ,  Katherine Saenger ,  Xiaoyan Shao

IPC分类号： H01L21/20

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US20050116230A1

公开(公告)日：2005-06-02

申请号：US10722557

申请日：2003-11-28

申请人： Cyril Cabral ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine Saenger

发明人： Cyril Cabral ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine Saenger

IPC分类号： H01L21/8238 ,  H01L27/108 ,  H01L29/49

CPC分类号： H01L29/4966 ,  H01L21/823842

摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

摘要翻译： 提供了包括至少一个FET的半导体器件，例如互补金属氧化物半导体（CMOS），其包括包含金属碳化物的栅电极和制造方法。 CMOS包括双功能金属栅电极，由此双功能功能由金属和金属的碳化物提供。

公开(公告)号：US20060186490A1

公开(公告)日：2006-08-24

申请号：US11372140

申请日：2006-03-10

申请人： Cyril Cabral ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine Saenger

发明人： Cyril Cabral ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine Saenger

IPC分类号： H01L29/94 ,  H01L29/76

CPC分类号： H01L29/4966 ,  H01L21/823842

摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

公开(公告)号：US20050196917A1

公开(公告)日：2005-09-08

申请号：US10790786

申请日：2004-03-03

申请人： Jingyu Lian ,  David Kotecki ,  Hua Shen ,  Robert Laibowitz ,  Katherine Saenger ,  Chenting Lin ,  Nicolas Nagel ,  Yunyu Wang ,  Satish Athavale ,  Thomas Shaw

发明人： Jingyu Lian ,  David Kotecki ,  Hua Shen ,  Robert Laibowitz ,  Katherine Saenger ,  Chenting Lin ,  Nicolas Nagel ,  Yunyu Wang ,  Satish Athavale ,  Thomas Shaw

IPC分类号： H01L21/8242

CPC分类号： H01L28/40 ,  H01L27/10852

摘要： A method for forming high capacitance crystalline dielectric layers with (111) texture is disclosed. In an exemplary embodiment, deposition of a plurality of nuclei is performed at a temperature in the range of about 430 to 460 degrees Celsius, followed by growth of a continuous BSTO dielectric layer at a temperature greater than 600 degrees Celsius. In an exemplary embodiment, a process is disclosed for growing a barium strontium titanium oxide film with high capacitance and thickness of about 30 nm or less.

摘要翻译： 公开了一种形成具有（111）结构的高电容结晶介电层的方法。 在一个示例性实施例中，多个核的沉积在约430至460摄氏度范围内的温度下进行，随后在大于600摄氏度的温度下生长连续的BSTO介电层。 在示例性实施例中，公开了用于生长具有约30nm或更小的高电容和厚度的钡锶氧化钛膜的方法。

公开(公告)号：US20070164337A1

公开(公告)日：2007-07-19

申请号：US11687000

申请日：2007-03-16

申请人： James Adkisson ,  Charles Black ,  Alfred Grill ,  Randy Mann ,  Deborah Neumayer ,  Wilbur Pricer ,  Katherine Saenger ,  Thomas Shaw

发明人： James Adkisson ,  Charles Black ,  Alfred Grill ,  Randy Mann ,  Deborah Neumayer ,  Wilbur Pricer ,  Katherine Saenger ,  Thomas Shaw

IPC分类号： H01L29/94

CPC分类号： H01L28/55 ,  H01L27/0629 ,  H01L27/11502 ,  H01L27/11507 ,  Y10S438/977

摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

摘要翻译： 提供了一种形成集成的铁电/ CMOS结构的方法，其有效地分离不兼容的高温沉积和退火工艺。 本发明的方法包括分别形成CMOS结构和铁电输送晶片。 然后使这些分离的结构与每个结构接触，并且通过使用低温退火步骤将输送晶片的铁电体膜结合到CMOS结构的上导电电极层。 然后去除输送晶片的一部分，提供集成的FE / CMOS结构，其中铁电电容器形成在CMOS结构的顶部。 电容器通过CMOS结构的所有布线级与CMOS结构的晶体管接触。

公开(公告)号：US20060275971A1

公开(公告)日：2006-12-07

申请号：US11406122

申请日：2006-04-18

申请人： Keith Fogel ,  Kam-Leung Lee ,  Katherine Saenger ,  Chun-Yung Sung ,  Haizhou Yin

发明人： Keith Fogel ,  Kam-Leung Lee ,  Katherine Saenger ,  Chun-Yung Sung ,  Haizhou Yin

IPC分类号： H01L21/26

CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/76224 ,  H01L21/823807

摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.

公开(公告)号：US20060244068A1

公开(公告)日：2006-11-02

申请号：US11116053

申请日：2005-04-27

申请人： Joel Desouza ,  Devendra Sadana ,  Katherine Saenger ,  Chun-yung Sung ,  Min Yang ,  Haizhou Yin

发明人： Joel Desouza ,  Devendra Sadana ,  Katherine Saenger ,  Chun-yung Sung ,  Min Yang ,  Haizhou Yin

IPC分类号： H01L27/12

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

摘要： Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.

摘要翻译： 混合定向衬底允许制造互补金属氧化物半导体（CMOS）电路，其中n型场效应晶体管（nFET）以优选的电子迁移率的半导体取向设置，并且p型场效应晶体管（pFET） 以半导体方向设置，其对于空穴迁移率是最佳的。 本发明公开了完全形成在最佳半导体取向中的FET的性能优点可以通过仅需要将器件的沟道设置在具有最佳取向的半导体中来实现。 描述了各种新的FET结构，其特征在于，至少部分FET通道的FET的源极和/或漏极的至少一部分具有不同的取向。 可以并入其中可并入这些新的FET的混合基板及其制造方法。

公开(公告)号：US20060154429A1

公开(公告)日：2006-07-13

申请号：US11031142

申请日：2005-01-07

申请人： Joel de Souza ,  Keith Fogel ,  John Ott ,  Devendra Sadana ,  Katherine Saenger

发明人： Joel de Souza ,  Keith Fogel ,  John Ott ,  Devendra Sadana ,  Katherine Saenger

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/2022

摘要： The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.

摘要翻译： 本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向 具有不同的方向。 更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶 非晶层的原始方向。 本发明方法的关键组分是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以去除在初始再结晶退火之后残留的缺陷。 本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。