公开(公告)号：US07919416B2

公开(公告)日：2011-04-05

申请号：US12357174

申请日：2009-01-21

Applicant: Woo-Jin Lee ,  Akira Shimizu ,  Atsuki Fukazawa

Inventor： Woo-Jin Lee ,  Akira Shimizu ,  Atsuki Fukazawa

IPC: H01L21/337

CPC classification number: C23C16/345 ,  C23C16/045 ,  C23C16/45523 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3185

Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film having Si—N bonds on the substrate.

Abstract translation: 通过等离子体增强化学气相沉积（PECVD）在半导体衬底上形成具有Si-N键的共形电介质膜的方法包括：将含氮和氢的反应气体和添加气体引入反应空间内， 底物放置; 向反应空间施加RF功率; 并将含氢的硅前体以脉冲方式引入到等离子体被激发的反应空间中，从而在衬底上形成具有Si-N键的保形电介质膜。

公开(公告)号：US07751851B2

公开(公告)日：2010-07-06

申请号：US10287197

申请日：2002-11-04

Applicant: Woo-Jin Lee ,  Yong-Nam Kim

Inventor： Woo-Jin Lee ,  Yong-Nam Kim

IPC: H04M1/00

CPC classification number: H04M1/72566 ,  H04M1/274575

Abstract: A method for managing a schedule as a supplementary function of a mobile communication terminal. The method is capable of efficiently managing schedule information such as anniversaries to be repeated every year. Further, the method is capable of conveniently making contact with another party by providing telephone numbers of the other party at the same time when the schedule information is provided to a user.

Abstract translation: 一种用于管理时间表作为移动通信终端的补充功能的方法。 该方法能够有效地管理每年要重复的周年纪念日程信息。 此外，该方法能够通过在将调度信息提供给用户的同时提供对方的电话号码来方便地与另一方进行联系。

公开(公告)号：US20090298257A1

公开(公告)日：2009-12-03

申请号：US12130522

申请日：2008-05-30

Applicant: Woo Jin Lee ,  Atsuki Fukazawa ,  Nobuo Matsuki

Inventor： Woo Jin Lee ,  Atsuki Fukazawa ,  Nobuo Matsuki

IPC: H01L21/31

CPC classification number: H01L21/76229 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/31604

Abstract: A method of forming device isolation regions on a trench-formed silicon substrate and removing residual carbon therefrom includes providing a flowable, insulative material constituted by silicon, carbon, nitrogen, hydrogen, oxygen or any combination of two or more thereof; forming a thin insulative layer, by using the flowable, insulative material, in a trench located on a semiconductor substrate wherein the flowable, insulative material forms a conformal coating in a silicon and nitrogen rich condition whereas in a carbon rich condition, the flowable, insulative material vertically grows from the bottom of the trenches; and removing the residual carbon deposits from the flowable, insulative material by multi-step curing, such as O2 thermal annealing, ozone UV curing followed by N2 thermal annealing.

Abstract translation: 在沟槽形成的硅衬底上形成器件隔离区并从中除去残留碳的方法包括提供由硅，碳，氮，氢，氧或其两种或多种的任何组合构成的可流动的绝缘材料; 通过在位于半导体衬底上的沟槽中使用可流动的绝缘材料形成薄的绝缘层，其中可流动的绝缘材料在富含硅和氮的条件下形成保形涂层，而在富含碳的条件下，可流动的，绝缘的 材料从沟槽的底部垂直生长; 并通过多步固化如O2热退火，臭氧UV固化，然后进行N2热退火，从可流动的绝缘材料中除去残留的碳沉积物。

公开(公告)号：US07622369B1

公开(公告)日：2009-11-24

申请号：US12130522

申请日：2008-05-30

Applicant: Woo Jin Lee ,  Atsuki Fukazawa ,  Nobuo Matsuki

Inventor： Woo Jin Lee ,  Atsuki Fukazawa ,  Nobuo Matsuki

IPC: H01L21/76 ,  H01L21/36 ,  H01L21/20 ,  H01L21/205 ,  H01L21/469

CPC classification number: H01L21/76229 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/31604

Abstract: A method of forming device isolation regions on a trench-formed silicon substrate and removing residual carbon therefrom includes providing a flowable, insulative material constituted by silicon, carbon, nitrogen, hydrogen, oxygen or any combination of two or more thereof; forming a thin insulative layer, by using the flowable, insulative material, in a trench located on a semiconductor substrate wherein the flowable, insulative material forms a conformal coating in a silicon and nitrogen rich condition whereas in a carbon rich condition, the flowable, insulative material vertically grows from the bottom of the trenches; and removing the residual carbon deposits from the flowable, insulative material by multi-step curing, such as O2 thermal annealing, ozone UV curing followed by N2 thermal annealing.

Abstract translation: 在沟槽形成的硅衬底上形成器件隔离区并从中除去残留碳的方法包括提供由硅，碳，氮，氢，氧或其两种或多种的任何组合构成的可流动的绝缘材料; 通过在位于半导体衬底上的沟槽中使用可流动的绝缘材料形成薄的绝缘层，其中可流动的绝缘材料在富含硅和氮的条件下形成保形涂层，而在富含碳的条件下，可流动的，绝缘的 材料从沟槽的底部垂直生长; 并通过多步固化如O2热退火，臭氧UV固化，然后进行N2热退火，从可流动的绝缘材料中除去残留的碳沉积物。

公开(公告)号：US20080056018A1

公开(公告)日：2008-03-06

申请号：US11896722

申请日：2007-09-05

Applicant: Joung-Yeal Kim ,  Jeong-Don Lim ,  Sung-Hoon Kim ,  Woo-Jin Lee

Inventor： Joung-Yeal Kim ,  Jeong-Don Lim ,  Sung-Hoon Kim ,  Woo-Jin Lee

IPC: G11C7/10

CPC classification number: G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C2207/107

Abstract: According to an example embodiment, a semiconductor memory device may include a memory core, input circuit, and/or an output circuit. The input circuit may be configured to generate second data from first data using latch circuits operating in response to input control signals enabled during different periods. The input circuit may be further configured to provide the second data to the memory core. The second data may have 2N times the number of bits of the first data, where N is a positive integer. The output circuit may be configured to generate fourth data from third data using latch circuits operating in response to output control signals enabled during different periods. The output circuit may be further configured to provide the fourth data to data output pins. The fourth data may have ½N times the number of bits of the third data. A method of inputting/outputting data is also provided.

Abstract translation: 根据示例实施例，半导体存储器件可以包括存储器芯，输入电路和/或输出电路。 输入电路可以被配置为使用响应于在不同周期期间启用的输入控制信号而工作的锁存电路从第一数据产生第二数据。 输入电路还可以被配置为向存储器核提供第二数据。 第二数据可以具有2N次第一数据的比特数，其中N是正整数。 输出电路可以被配置为使用响应于在不同周期期间启用的输出控制信号而工作的锁存电路从第三数据生成第四数据。 输出电路还可以被配置为向数据输出引脚提供第四数据。 第四数据可以具有第三数据的比特数的1/2N倍。 还提供了一种输入/输出数据的方法。

公开(公告)号：US20060290386A1

公开(公告)日：2006-12-28

申请号：US11430111

申请日：2006-05-09

Applicant: Woo-jin Lee ,  Sung-hoon Kim

Inventor： Woo-jin Lee ,  Sung-hoon Kim

IPC: H03K19/094

CPC classification number: H03K19/0948 ,  H03K19/09432

Abstract: A NAND gate, a NOR gate, an output buffer and method thereof. An example embodiment of the present invention is directed to a NAND gate, including a first transistor having a source to which a supply voltage is applied and a gate to which a ground voltage is applied, a first plurality of transistors connected in series between the first transistor and the ground voltage, gates of the first plurality of transistors receiving a first input signal, the first plurality of transistors including at least three transistors and a second plurality of transistors connected in series between the first transistor and the ground voltage, the second plurality of transistors not in series with the first plurality of transistors and including at least three transistors. Another example embodiment of the present invention is directed to a NOR gate including a first plurality of transistors connected in series with a supply voltage, the first plurality of transistors including first, second and third transistors, a second plurality of transistors connected in series with the supply voltage and not connected in series with the first plurality of transistors, the second plurality of transistors including fourth, fifth and sixth transistors and a seventh transistor connected between the third and sixth transistors and a ground voltage and having a gate connected to the supply voltage. The example NOR and NAND gates may be employed within the example output buffer. The example NOR and NAND gates may also be employed in the example method so as to reduce skew by attaining the same output characteristics.

Abstract translation: NAND门，或非门，输出缓冲器及其方法。 本发明的示例性实施例涉及一种与非门，其包括具有施加电源电压的源极和施加了接地电压的栅极的第一晶体管，串联连接在第一晶体管的第一晶体管 晶体管和接地电压，第一多个晶体管的栅极接收第一输入信号，第一多个晶体管包括至少三个晶体管和串联连接在第一晶体管和接地电压之间的第二多个晶体管，第二多个晶体管 的晶体管不与第一多个晶体管串联并且包括至少三个晶体管。 本发明的另一示例性实施例涉及包括与电源电压串联连接的第一多个晶体管的或非门，第一多个晶体管包括第一，第二和第三晶体管，第二多个晶体管与 电源电压并且不与第一多个晶体管串联连接，第二多个晶体管包括第四，第五和第六晶体管，以及连接在第三和第六晶体管之间的第七晶体管和接地电压，并且具有连接到电源电压的栅极 。 示例性的NOR和NAND门可以在示例性输出缓冲器内使用。 示例性的NOR和NAND门也可以用于示例性方法中，以便通过获得相同的输出特性来减少偏斜。

公开(公告)号：US20060255829A1

公开(公告)日：2006-11-16

申请号：US11429296

申请日：2006-05-05

Applicant: Hyun-Jin Kim ,  Kwang-Il Park ,  Woo-Jin Lee

Inventor： Hyun-Jin Kim ,  Kwang-Il Park ,  Woo-Jin Lee

IPC: H03K17/16

CPC classification number: G06F13/4072 ,  H04L25/0278 ,  H04L25/028

Abstract: A semiconductor memory device includes a primary output driver which outputs a data signal through an output terminal; a secondary output driver which is connected to the output terminal and performs a pre-emphasis operation; and a pre-emphasis signal generator which outputs a pre-emphasis signal to enable the secondary output driver The pre-emphasis signal generator includes a auto pulse generator which generates an auto pulse in response to a transition of a control signal; a delay circuit which receives the auto pulse output from the auto pulse generator, delays the auto pulse by a predetermined period, and outputs a pre-emphasis signal; and a delay control unit which applies a delay control signal to the delay circuit and controls a delay amount of the delay circuit.

Abstract translation: 半导体存储器件包括通过输出端输出数据信号的初级输出驱动器; 二次输出驱动器，其连接到输出端子并执行预加重操作; 以及预加重信号发生器，其输出预加重信号以使得辅助输出驱动器。预加重信号发生器包括自动脉冲发生器，其响应于控制信号的转变而产生自动脉冲; 接收从自动脉冲发生器输出的自动脉冲的延迟电路将自动脉冲延迟预定周期，并输出预加重信号; 以及延迟控制单元，其向延迟电路施加延迟控制信号并控制延迟电路的延迟量。

公开(公告)号：US08932964B2

公开(公告)日：2015-01-13

申请号：US13444054

申请日：2012-04-11

Applicant: Woo-Jin Lee ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Hyun-Bae Lee

Inventor： Woo-Jin Lee ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Hyun-Bae Lee

IPC: H01L21/31 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/02359 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a dielectric layer, the method including sequentially forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate by performing a plasma-enhanced atomic layer deposition process, wherein a first nitrogen plasma treatment is performed after forming the first oxide layer.

Abstract translation: 一种形成电介质层的方法，所述方法包括通过执行等离子体增强原子层沉积工艺在衬底上顺序地形成第一氧化物层，氮化物层和第二氧化物层，其中第一氮等离子体处理在 形成第一氧化物层。

公开(公告)号：US08557217B2

公开(公告)日：2013-10-15

申请号：US12310615

申请日：2007-09-11

Applicant: Insoo Kim ,  Woo Jin Lee ,  Young Jin Kim ,  Charles E. Smith, Jr.

Inventor： Insoo Kim ,  Woo Jin Lee ,  Young Jin Kim ,  Charles E. Smith, Jr.

IPC: C01G23/053 ,  C01B15/01

CPC classification number: C01G23/053 ,  B82Y30/00 ,  C01G23/0532 ,  C01G23/0536 ,  C01P2002/72 ,  C01P2004/03 ,  C01P2004/50 ,  C01P2004/64

Abstract: A process for synthesizing nano-sized rutile, anatase, or a mixture of rutile and anatase TiO2 powder. The process includes the steps of: 1) forming a Ti-peroxo complex by mixing H2O2 with a Ti compound, and 2) heating the Ti-peroxo complex at a temperature of above 50° C. A primary particle size of TiO2 particles, synthesized by the method, is below 50 nm, and an agglomerated particle size thereof after a washing/dry process is below about 10 μm. The major characteristics of the present invention are that it is a low temperature process, a highly concentrated synthesis, and high production yield of above 90%.

Abstract translation: 合成纳米尺寸金红石，锐钛矿或金红石和锐钛矿TiO 2粉末的混合物的方法。 该方法包括以下步骤：1）通过将H 2 O 2与Ti化合物混合形成Ti-过氧配合物，和2）在高于50℃的温度下加热Ti-过氧配合物。合成的TiO 2颗粒的一次粒径 通过该方法，低于50nm，洗涤/干燥处理后的附聚粒径低于约10μm。 本发明的主要特征是低温工艺，高浓缩合成，高产率高于90％。

公开(公告)号：US20130093699A1

公开(公告)日：2013-04-18

申请号：US13572743

申请日：2012-08-13

Applicant: Jinuk Lee ,  Sang Su Hong ,  Woo Jin Lee ,  Dong Hwan Lee

Inventor： Jinuk Lee ,  Sang Su Hong ,  Woo Jin Lee ,  Dong Hwan Lee

IPC: G06F3/041

CPC classification number: G06F3/041 ,  G06F3/044 ,  G06F2203/04103

Abstract: Disclosed herein is a touch panel. The touch panel 100 according to the present invention includes electrode patterns 110 disposed in parallel with each other in a first direction (A), wherein the electrode patterns are provided with opening portions 120 dividing the electrode patterns 110 into two portions, the opening portions 120 having a configuration 125 in which the opening portion moves N times in the first direction (A) while going to a second direction (B) that is vertical to the first direction (A), the configuration 125 being repeated M times. The touch panel allows the electrode patterns to have a single-layer structure by adopting the opening portions 120 in the electrode patterns 110, thereby making it possible to reduce the manufacturing costs of the touch panel and simplify the manufacturing process thereof.

Abstract translation: 这里公开了触摸面板。 根据本发明的触摸面板100包括在第一方向（A）上彼此平行设置的电极图案110，其中电极图案设置有将电极图案110分成两部分的开口部分120，开口部分120 具有其中开口部分沿着与第一方向（A）垂直的第二方向（B）在第一方向（A）移动N次的配置125，配置125重复M次。 触摸面板通过采用电极图案110中的开口部分120来允许电极图案具有单层结构，从而可以降低触摸面板的制造成本并简化其制造工艺。