公开(公告)号：US20160116964A1

公开(公告)日：2016-04-28

申请号：US14986677

申请日：2016-01-02

Applicant: Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC: G06F1/32 ,  G06F9/50 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

公开(公告)号：US20160116963A1

公开(公告)日：2016-04-28

申请号：US14986676

申请日：2016-01-02

Applicant: Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC: G06F1/32 ,  G06F9/50

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

Abstract translation: 可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。 可以用信号通知第二处理核心的加电。 可以收集执行程序代码的第一处理核心的第一性能度量。 当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。 当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

公开(公告)号：US09152417B2

公开(公告)日：2015-10-06

申请号：US13996610

申请日：2011-09-27

Applicant: Cheng Wang ,  Youfeng Wu

Inventor： Cheng Wang ,  Youfeng Wu

IPC: G06F9/45 ,  G06F9/30 ,  G06F9/455 ,  G06F9/38

CPC classification number: G06F9/30098 ,  G06F8/434 ,  G06F8/4441 ,  G06F9/3834 ,  G06F9/45516

Abstract: Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for expediting execution time memory alias checking. A sequence of instructions targeted for execution on an execution processor may be received or retrieved. The execution processor may include a plurality of alias registers and circuitry configured to check entries in the alias register for memory aliasing. One or more optimizations may be performed on the received or retrieved sequence of instructions to optimize execution performance of the received or retrieved sequence of instructions. This may include a reorder of a plurality of memory instructions in the received or retrieved sequence of instructions. After the optimization, one or more move instructions may be inserted in the optimized sequence of instructions to move one or more entries among the alias registers during execution, to expedite alias checking at execution time. Other embodiments may be described and/or claimed.

Abstract translation: 本文描述了装置，计算机实现的方法，系统和计算机可读介质的实施例，用于加速执行时间存储器别名检查。 可以接收或检索针对执行处理器执行的指令序列。 执行处理器可以包括多个别名寄存器和被配置为检查别名寄存器中的条目以用于存储器混叠的电路。 可以对所接收或检索的指令序列执行一个或多个优化，以优化所接收或检索的指令序列的执行性能。 这可以包括在接收或检索的指令序列中的多个存储器指令的重排序。 在优化之后，可以在优化的指令序列中插入一个或多个移动指令以在执行期间移动别名寄存器中的一个或多个条目，以在执行时加速别名检查。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150277866A1

公开(公告)日：2015-10-01

申请号：US14225755

申请日：2014-03-26

Applicant: Cheng Wang ,  Youfeng Wu ,  Hongbo Rong ,  Hyunchul Park

Inventor： Cheng Wang ,  Youfeng Wu ,  Hongbo Rong ,  Hyunchul Park

IPC: G06F9/45 ,  G06F9/455

CPC classification number: G06F9/45516 ,  G06F9/4411 ,  G06F9/4552 ,  G06F13/10

Abstract: In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括至少一个核心和动态语言加速器，以响应于与动态语言加速器相关联的文件描述符的存储器映射的输入/输出（MMIO）操作来执行字节码。 当动态语言加速器执行字节码时，处理器可能会阻止本地代码的执行。 描述和要求保护其他实施例。

公开(公告)号：US20150039861A1

公开(公告)日：2015-02-05

申请号：US14126466

申请日：2013-05-30

Applicant: Hongbo Rong ,  Cheng Wang ,  Hyunchul Park ,  Youfeng Wu

Inventor： Hongbo Rong ,  Cheng Wang ,  Hyunchul Park ,  Youfeng Wu

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3838 ,  G06F8/434 ,  G06F8/441 ,  G06F8/443 ,  G06F9/30127 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/384

Abstract: In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，系统包括处理器，其包括一个或多个核和多个别名寄存器，用于存储与循环的多个操作相关联的存储器范围信息。 存储器范围信息引用存储器内的一个或多个存储器位置。 该系统还包括寄存器分配装置，用于将每个别名寄存器分配给循环的对应操作，其中根据旋转调度进行分配，并且在第一次迭代中将一个别名寄存器分配给第一操作 循环和循环的后续迭代中的第二操作。 该系统还包括耦合到处理器的存储器。 描述和要求保护其他实施例。

公开(公告)号：US20140359591A1

公开(公告)日：2014-12-04

申请号：US14126463

申请日：2013-05-30

Applicant: Hyunchul Park ,  Hongbo Rong ,  Youfeng Wu

Inventor： Hyunchul Park ,  Hongbo Rong ,  Youfeng Wu

IPC: G06F9/45

CPC classification number: G06F8/4452 ,  G06F8/441 ,  G06F8/443 ,  G06F8/4451 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3863

Abstract: In an embodiment, a system includes a processor including at least one core to execute operations of a loop that includes S stages. The system also includes stage insertion means for adding a delay stage to the loop to increase a lifetime of a corresponding register associated with a first variable of the loop and to delay storage of contents of the register. The system also includes a dynamic random access memory (DRAM). Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，系统包括处理器，其包括至少一个核，以执行包括S级的循环的操作。 该系统还包括阶段插入装置，用于向环路增加延迟级，以增加与循环的第一变量相关联的相应寄存器的寿命并延迟存储寄存器的内容。 该系统还包括动态随机存取存储器（DRAM）。 描述和要求保护其他实施例。

公开(公告)号：US20140032885A1

公开(公告)日：2014-01-30

申请号：US14041170

申请日：2013-09-30

Applicant: Edson Borin ,  Youfeng Wu

Inventor： Edson Borin ,  Youfeng Wu

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863

Abstract: Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.

Abstract translation: 公开了用于管理部分提交检查点的示例性方法和装置。 所公开的示例性方法包括识别与由处理器执行的指令区域相关联的提交指令，从指令区域识别候选指令，以及生成处理器部分提交检查点以保存处理器的当前状态，所述检查点基于 与实时指令相关联的计算寄存器值，并包括链接候选指令的指令参考地址。

公开(公告)号：US20130318507A1

公开(公告)日：2013-11-28

申请号：US13893238

申请日：2013-05-13

Applicant: Mauricio Breternitz, JR. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

Inventor： Mauricio Breternitz, JR. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

IPC: G06F11/36

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 本文描述了用于有条件地提交和/或推测性检查点事务的装置和方法，这可能导致事务的动态调整大小。 在二进制代码的动态优化期间，插入事务以提供内存排序保护措施，这使得动态优化器能够更积极地优化代码。 并且条件提交可以有效地执行动态优化代码，同时尝试防止事务用尽硬件资源。 虽然投机检查点能够在中止交易后快速有效地恢复。 处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。 并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。

公开(公告)号：US08549504B2

公开(公告)日：2013-10-01

申请号：US12890639

申请日：2010-09-25

Applicant: Mauricio Breternitz, Jr. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

Inventor： Mauricio Breternitz, Jr. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

IPC: G06F9/45

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：US08522223B2

公开(公告)日：2013-08-27

申请号：US11603375

申请日：2006-11-22

Applicant: Cheng Wang ,  Youfeng Wu ,  Wei-Yu Chen ,  Zhiwei Ying

Inventor： Cheng Wang ,  Youfeng Wu ,  Wei-Yu Chen ,  Zhiwei Ying

IPC: G06F9/45

CPC classification number: G06F9/466 ,  G06F8/41

Abstract: In general, in one aspect, the disclosure describes a method to detect a transaction and direct non transactional memory (TM) user functions within the transaction. The non TM user functions are treated as TM functions and added to the TM list.

Abstract translation: 通常，在一个方面，本公开描述了一种检测事务中的交易和直接非事务性存储器（TM）用户功能的方法。 非TM用户功能被视为TM功能并添加到TM列表中。