Abstract:
An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.
Abstract:
A display may be provided with integral touch functionality. The display may include a common electrode layer having row electrodes arranged in rows and column electrodes interposed between the row electrodes of each row. The row electrodes may be electrically coupled by conductive paths. The row and column electrodes may be coupled to touch sensor circuitry that uses the row and column electrodes to detect touch events. Each electrode of the common electrode layer may cover a respective portion of an array of pixels. Each pixel of the display may have a respective aperture. The conductive paths that electrically couple row electrodes of the common electrode layer may cover or otherwise block some light from passing through pixels, resulting in reduced apertures. Dummy structures may be provided for other pixels that modify the apertures of the other pixels to match the reduced apertures associated with the conductive paths.
Abstract:
An electronic device display may have an array of display pixels that are controlled using a grid of data lines and gate lines. The display may include compact gate driver circuits that perform gate driver operations to drive corresponding gate lines. Each compact gate driver circuit may include a first driver stage and a second driver stage. The first driver stage may receive a start pulse signal and produce a control signal. The control signal may be stored by a capacitor to identify a control state of the gate driver circuit. The second driver stage may receive the control signal, a clock signal, and a corresponding inverted clock signal and drive the corresponding gate line based on the received signals. The second driver stage may include pass transistor circuitry that passes the clock signal to the corresponding gate line and may include short circuit protection circuitry.
Abstract:
A transistor that may be used in electronic displays to selectively activate one or more pixels. The transistor includes a metal layer, a silicon layer deposited on at least a portion of the metal layer, the silicon layer includes an extension portion that extends a distance past the metal layer, and at least three lightly doped regions positioned in the silicon layer. The at least three lightly doped regions have a lower concentration of doping atoms than other portions of the silicon layer forming the transistor.
Abstract:
An electronic device may include a display and a sensor under the display. The display may include an array of subpixels for displaying an image to a user of the electronic device. At least a portion of the array of subpixels may be selectively removed in a pixel removal region to improve optical transmittance to the sensor through the display. The pixel removal region may include a plurality of pixel free regions that are devoid of thin-film transistor structures, that are devoid of power supply lines, that have continuous open areas due to rerouted row/column lines, that are partially devoid of touch circuitry, that optionally include dummy contacts, and/or have selectively patterned display layers.
Abstract:
A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.
Abstract:
A display may include pixels arranged in rows and columns in an active area and display driver circuitry in an inactive area. Data lines for the pixels may be positioned in the active area. Fanout lines may be routed through the active area. Each fanout line may electrically connect the display driver circuitry to a respective data line. One or more pixels may include a drive transistor and a light-emitting diode that are connected in series between a first power supply terminal and a second power supply terminal. A conductive layer may form a first terminal (such as the source terminal, the gate terminal, or the drain terminal) for the drive transistor. A conductive shielding layer may be interposed between the conductive layer and a fanout line to mitigate capacitive coupling between the terminal of the drive transistor and the fanout line.
Abstract:
To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.
Abstract:
An electronic device may include a display having display pixels formed in an active area of the display. The display further includes display driver circuitry for driving gate lines that are routed across the display. A hole such as a through hole, optical window, or other inactive region may be formed within the active area of the display. Multiple gate lines carrying the same signal may be merged together prior to being routed around the hole to help minimize the routing line congestion around the border of the hole. Dummy circuits may be coupled to the merged segment portion to help increase the parasitic loading on the merged segments. The hole may have a tapered shape to help maximize the size of the active area. The hole may have an asymmetric shape to accommodate multiple sub-display sensor components.
Abstract:
A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.