公开(公告)号：US20080254374A1

公开(公告)日：2008-10-16

申请号：US12061954

申请日：2008-04-03

申请人： Satoru YAMADA ,  Makoto Kamo ,  Toshio Sasaki

发明人： Satoru YAMADA ,  Makoto Kamo ,  Toshio Sasaki

IPC分类号： G03F7/00

CPC分类号： G11B7/245 ,  G11B7/00781 ,  G11B7/24044 ,  G11B7/244 ,  G11B7/2492 ,  G11B7/2533 ,  G11B7/2534 ,  G11B7/2536 ,  G11B7/2585

摘要： The present invention provides a holographic recording composition and a holographic recording medium comprising a recording layer formed with the holographic recording composition. The holographic recording composition comprises a bifunctional or greater isocyanate, a polyfunctional alcohol comprising a bifunctional alcohol and a trifunctional or greater alcohol, a titanocene-based radical polymerization initiator, a bifunctional or greater acrylate monomer, and an amidine salt denoted by General Formula (1). In General Formula (1), R1, R2, and R3 each independently denote an alkyl group, aryl group, amino group, or acyl group, R1 and R2 may be bonded together to form a ring, R2 and R3 may be bonded together to form a ring, and A− denotes an anion.

摘要翻译： 本发明提供一种全息记录组合物和全息记录介质，其包括由全息记录组合物形成的记录层。 全息记录组合物包含双官能或更大的异氰酸酯，包含双官能醇和三官能以上醇的多官能醇，二茂钛基自由基聚合引发剂，双官能或更高级丙烯酸酯单体和由通式（1）表示的脒盐 ）。 在通式（1）中，R 1，R 2，R 3和R 3各自独立地表示烷基，芳基，氨基， 或酰基，R 1和R 2可以结合在一起形成环，R 2和R 3 >可以键合在一起以形成环，并且“A”表示阴离子。

公开(公告)号：US20080219082A1

公开(公告)日：2008-09-11

申请号：US12046150

申请日：2008-03-11

申请人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

发明人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC分类号： G11C8/06 ,  G11C8/10

CPC分类号： G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

摘要翻译： 公开了一种非易失性存储器系统，包括至少一个非易失性存储器，每个非易失性存储器具有多个非易失性存储单元和缓冲存储器; 以及耦合到所述非易失性存储器的控制装置。 控制装置能够接收外部数据并将数据应用于非易失性存储器，并且使非易失性存储器能够操作程序操作，包括将接收到的数据存储到缓冲存储器并将保存在缓冲存储器中的数据存储到缓冲存储器中 的非易失性存储单元。 此外，控制装置能够在非易失性存储器在程序操作中操作时接收外部数据。 此外，缓冲存储器能够接收与程序运行一次要存储的数据的数据长度相等的数据单位，数据长度大于1字节。

公开(公告)号：US20070223348A1

公开(公告)日：2007-09-27

申请号：US11727061

申请日：2007-03-23

申请人： Toshio Sasaki

发明人： Toshio Sasaki

IPC分类号： G11B7/00

CPC分类号： G11B7/0065 ,  G03H1/16 ,  G11B7/00781 ,  G11B7/24044 ,  G11B7/2405 ,  G11B7/245 ,  G11B7/246 ,  G11B7/2463 ,  G11B7/252 ,  G11B7/2585 ,  G11B7/26 ,  G11B20/1217 ,  G11B27/10 ,  G11B27/3027 ,  G11B2020/1287 ,  G11B2220/2504

摘要： To provide an optical recording method including: applying information and reference beams onto an optical recording medium to record information therein, the optical recording medium having a recording layer for recording the information by holography, wherein at least the information beam is passed through a spatial light modulator and is formed as a two-dimensional pattern composed of a data area and a plurality of synchronization marks for detecting information concerning the positions of data recorded in the data area, and wherein the synchronization marks are arranged in a random pattern so that in a Fourier-transformed image of the two-dimensional pattern, light intensities derived from the synchronization marks are lower than light intensities in a Fourier-transformed image of a two-dimensional pattern composed of a data area and a plurality of synchronization marks arranged in a grid pattern, the light intensities being derived from the synchronization marks arranged in a grid pattern.

摘要翻译： 为了提供一种光学记录方法，包括：将信息和参考光束应用到光学记录介质上以在其中记录信息，所述光学记录介质具有用于通过全息记录信息的记录层，其中至少信息光束通过空间光 并且形成为由数据区域和多个同步标记组成的二维图案，用于检测关于记录在数据区域中的数据的位置的信息，并且其中同步标记以随机图案排列，使得在 二维图案的傅里叶变换图像，从同步标记导出的光强度低于由数据区域和布置在网格中的多个同步标记组成的二维图案的傅里叶变换图像中的光强度 模式，光强度从布置在网格中的同步标记导出 模式

公开(公告)号：US20070004092A1

公开(公告)日：2007-01-04

申请号：US10569735

申请日：2003-08-29

申请人： Hiromichi Suzuki ,  Fujio Ito ,  Toshio Sasaki

发明人： Hiromichi Suzuki ,  Fujio Ito ,  Toshio Sasaki

IPC分类号： H01L21/00

CPC分类号： H01L24/83 ,  H01L21/565 ,  H01L23/4334 ,  H01L23/49558 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05599 ,  H01L2924/00012

摘要： This manufacturing method of a semiconductor device prepares a lead frame to which a heat spreader, and the tip parts of a plurality of inner leads were joined via a thermoplastic insulating binding material, arranges a lead frame on a heat stage, and joins the semiconductor chip to the heat spreader via the thermoplastic binding material which was heated and softened after having arranged the semiconductor chip on the heat spreader. Die bonding can be performed without scattering inner leads by joining the semiconductor chip and the thermoplastic binding material, suppressing the tip parts of the inner leads to the heat stage side. Improvement in the assembling property of a semiconductor device can be aimed at.

摘要翻译： 这种半导体装置的制造方法准备一个引线框架，散热器和多个内部引线的末端部分通过热塑性绝缘粘合材料接合，将引线框架布置在热台上，并连接半导体芯片 通过在将散热器上布置半导体芯片之后被加热和软化的热塑性粘合材料到散热器。 可以通过接合半导体芯片和热塑性粘合材料而不会使内部引线散射，从而将内部引线的顶端部分抑制到加热台侧来进行晶片接合。 可以针对半导体器件的组装性能的改进。

公开(公告)号：US20070001271A1

公开(公告)日：2007-01-04

申请号：US10569577

申请日：2003-08-29

申请人： Fujio Ito ,  Hiromichi Suzuki ,  Toshio Sasaki

发明人： Fujio Ito ,  Hiromichi Suzuki ,  Toshio Sasaki

IPC分类号： H01L23/495

CPC分类号： H01L23/49541 ,  H01L21/4842 ,  H01L23/49558 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion of the inner lead groups which adjoin among four inner lead groups corresponding to each side of the bar lead, and was connected with the bar lead, and a tape member joined to the tip part of each inner lead, a bar lead, and a corner part lead are included. Since the corner part lead is formed as an object for reinforcement of a frame body between adjoining inner lead groups, the rigidity of the lead frame can be increased.

摘要翻译： 多个内部引线，多个外部引线，每个外部引线与内部引线中的每一个形成一个，方形环形状的引脚布置在多个内部引线内;角部引线，其设置在内部引线之间 所述内引线组的与所述棒引线的每一侧相对应的四个内引线组中相邻的所述内引线组的端部与所述引线连接，以及与所述内引线的前端接合的带部件， 并包括角落部分铅。 由于角部引线形成为在相邻的内引线组之间加强框架体的对象，所以可以提高引线框架的刚性。

公开(公告)号：US07073147B2

公开(公告)日：2006-07-04

申请号：US10694825

申请日：2003-10-29

申请人： Hiroyuki Ikeda ,  Toshio Sasaki ,  Akinobu Watanabe ,  Toshio Yamada ,  Akihisa Uchida

发明人： Hiroyuki Ikeda ,  Toshio Sasaki ,  Akinobu Watanabe ,  Toshio Yamada ,  Akihisa Uchida

IPC分类号： G06F17/50

CPC分类号： H01L27/11 ,  G11C5/14 ,  H01L27/0207

摘要： Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.

摘要翻译： 连接到用于衬底偏置电路的从属开关电路单元的栅电极的布线分别电连接到用于电源电位的布线和用于参考电位的布线。 因此，从开关电路单元的开关动作无效。 连接到各个电路单元的n个阱的布线电连接到用于电源电位的布线，并且连接到各个电路单元的p阱的布线电连接到布线。 因此，n个阱被固定到电源电位，并且p阱被固定到参考电位。

公开(公告)号：US06967881B2

公开(公告)日：2005-11-22

申请号：US10785101

申请日：2004-02-25

申请人： Toshio Sasaki ,  Toshio Yamada

发明人： Toshio Sasaki ,  Toshio Yamada

IPC分类号： H01L21/822 ,  G11C16/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H03K19/00 ,  G11C11/00

CPC分类号： G11C29/802 ,  G11C16/0441 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12005 ,  G11C2029/1208 ,  G11C2029/4402 ,  H01L27/115 ,  H01L2223/5444

摘要： A semiconductor integrated circuit makes use of nonvolatile memory cells of a fuse circuit connected to a dedicated signal line without using a nonvolatile memory intended for general purpose use, which is connected to a common bus, in order to store control information for defect relief and the like of circuit modules. The reliability of storage of the control information is not limited to the performance of storage of information in the nonvolatile memory intended for general purpose use, and the reliability of storage of the control information can be easily enhanced. Since a second wiring used in the transfer of the control information is of a wiring dedicated for its transfer, it needs not perform switching between connections to circuit portions used for actual operations in the circuit modules and their control. A circuit configuration for delivering the control information can be simplified.

摘要翻译： 半导体集成电路使用连接到专用信号线的熔丝电路的非易失性存储单元，而不使用连接到公共总线的旨在用于通用的非易失性存储器，以便存储用于缺陷消除的控制信息，并且 像电路模块一样。 控制信息的存储的可靠性不限于旨在用于通用目的的非易失性存储器中的信息的存储性能，并且可以容易地增强控制信息的存储的可靠性。 由于用于传送控制信息的第二布线是专用于其传送的布线，所以不需要在用于电路模块中的实际操作的电路部分的连接和它们的控制之间进行切换。 可以简化用于传送控制信息的电路配置。

公开(公告)号：US06762969B2

公开(公告)日：2004-07-13

申请号：US10346097

申请日：2003-01-17

申请人： Toshio Sasaki ,  Toshio Yamada

发明人： Toshio Sasaki ,  Toshio Yamada

IPC分类号： G11C700

CPC分类号： G11C29/802 ,  G11C16/0441 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12005 ,  G11C2029/1208 ,  G11C2029/4402 ,  H01L27/115 ,  H01L2223/5444

摘要： A semiconductor integrated circuit makes use of nonvolatile memory cells of a fuse circuit connected to a dedicated signal line without using a nonvolatile memory intended for general purpose use, which is connected to a common bus, in order to store control information for defect relief and the like of circuit modules. The reliability of storage of the control information is not limited to the performance of storage of information in the nonvolatile memory intended for general purpose use, and the reliability of storage of the control information can be easily enhanced. Since a second wiring used in the transfer of the control information is of a wiring dedicated for its transfer, it needs not perform switching between connections to circuit portions used for actual operations in the circuit modules and their control. A circuit configuration for delivering the control information can be simplified.

摘要翻译： 半导体集成电路使用连接到专用信号线的熔丝电路的非易失性存储单元，而不使用连接到公共总线的旨在用于通用的非易失性存储器，以便存储用于缺陷消除的控制信息，并且 像电路模块一样。 控制信息的存储的可靠性不限于旨在用于通用目的的非易失性存储器中的信息的存储性能，并且可以容易地增强控制信息的存储的可靠性。 由于用于传送控制信息的第二布线是专用于其传送的布线，所以不需要在用于电路模块中的实际操作的电路部分的连接和它们的控制之间进行切换。 可以简化用于传送控制信息的电路配置。

公开(公告)号：US06738310B2

公开(公告)日：2004-05-18

申请号：US10351524

申请日：2003-01-27

申请人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

发明人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC分类号： G11C700

CPC分类号： G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

公开(公告)号：US06480425B2

公开(公告)日：2002-11-12

申请号：US09820972

申请日：2001-03-30

申请人： Kazumasa Yanagisawa ,  Toshio Sasaki ,  Satoru Nakanishi ,  Yoshihiko Yasu

发明人： Kazumasa Yanagisawa ,  Toshio Sasaki ,  Satoru Nakanishi ,  Yoshihiko Yasu

IPC分类号： G11C700

CPC分类号： G11C11/4091 ,  G11C5/025 ,  G11C7/065

摘要： A dynamic RAM includes sense amplifiers each formed of a latch circuit consisting of MOSFETs of a first and second conductivity types with the application of a first and second voltages to the sources thereof, respectively, and having a pair of input/output nodes corresponding to a first bit line pair which is connected with a number of dynamic memory cells, and further includes pairs of switching MOSFETs of the first conductivity type which connect selectively an input/output node pair of the latch circuits to a pair of second bit lines provided commonly to a plurality of the first bit line pair in response to the reception of the select signal. The switching MOSFETs have their threshold voltage set smaller in terms of absolute value than the threshold voltage of the MOSFETs of the first conductivity type of the latch circuits, and the select signal has its level of turning off the switching MOSFETs set greater in terms of absolute value than the first voltage with respect to the second voltage.

摘要翻译： 动态RAM包括读出放大器，每个读出放大器分别由一个由第一和第二导电类型的MOSFET构成的锁存电路构成，并分别对其源极施加第一和第二电压，并具有一对输入/输出节点 第一位线对与多个动态存储单元连接，并且还包括成对的第一导电类型的开关MOSFET，其选择性地将锁存电路的输入/输出节点对连接到一对共同设置的第二位线 多个第一位线对响应于该选择信号的接收。 开关MOSFET的阈值电压设置为比第一导电类型的锁存电路的MOSFET的阈值电压的绝对值小，并且选择信号具有关闭开关MOSFET的电平，该开关MOSFET的绝对值设定得更大 相对于第二电压的第一电压值。