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170 条记录 (耗时 0.035 秒)

    TEOS assisted oxide CMP process
    51.
    发明授权
    TEOS assisted oxide CMP process 失效
    TEOS辅助氧化物CMP工艺

    公开(公告)号：US07091103B2

    公开(公告)日：2006-08-15

    申请号：US10314865

    申请日：2002-12-09

    申请人： Jochen Beintner ,  Laertis Economikos ,  Michael Wise ,  Andreas Knorr

    发明人： Jochen Beintner ,  Laertis Economikos ,  Michael Wise ,  Andreas Knorr

    IPC分类号： H01L21/76 ,  H01L21/461 ,  H01L21/302

    CPC分类号： H01L21/76819 ,  H01L21/31053 ,  H01L21/31055 ,  H01L27/1087 ,  H01L27/10894

    摘要： CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.

    摘要翻译： 包含具有沟槽电容器的DRAM阵列的集成电路的CMP用氧化物填充沟槽，导致与周围的支撑结构中的浓度相比密集的氧化物结构的阵列，因此具有更高的负载。 保形层沉积在晶片上，增加阵列中的负载，但填充有效区域之间的空间。 覆盖蚀刻去除阵列和支撑体中的材料。 块蚀刻平衡阵列中的材料和支撑体的数量。 阵列中的补充氧化物沉积将结构之间的空间填充到几乎均匀的密度。

    Structure and method for improved isolation in trench storage cells
    52.
    发明授权
    Structure and method for improved isolation in trench storage cells 失效
    用于改善沟槽存储单元隔离的结构和方法

    公开(公告)号：US06437401B1

    公开(公告)日：2002-08-20

    申请号：US09824957

    申请日：2001-04-03

    申请人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

    发明人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

    IPC分类号： H01L2976

    CPC分类号： H01L27/1087 ,  H01L27/10861 ,  H01L27/10864 ,  H01L29/945

    摘要： A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.

    摘要翻译： 提供了用于改善电荷保留的沟槽电容器结构及其制造方法。 在p型导电性半导体衬底中形成沟槽。 隔离套环位于沟槽的上部。 与沟槽上部相邻的衬底包含第一n +型导电区​​和第二n +型导电区​​。 这些区域各自邻接沟槽的壁并且被p型导电性半导体衬底的一部分垂直分开。 围绕沟槽的周边的空隙形成沟槽的壁，并且位于第一和第二n +型导电区​​域之间的衬底中。

    Method for forming and filling isolation trenches
    53.
    发明授权
    Method for forming and filling isolation trenches 有权
    用于形成和填充隔离沟槽的方法

    公开(公告)号：US06294423B1

    公开(公告)日：2001-09-25

    申请号：US09718211

    申请日：2000-11-21

    申请人： Rajeev Malik ,  Mihel Seitz ,  Andreas Knorr

    发明人： Rajeev Malik ,  Mihel Seitz ,  Andreas Knorr

    IPC分类号： H01L218242

    CPC分类号： H01L21/76229 ,  H01L27/1087

    摘要： A method for forming isolation trenches for a semiconductor device forms, in a substrate, a plurality of trenches having different widths including widths above a threshold size and widths below a threshold size. The plurality of trenches have a same first depth. A masking layer is deposited in the plurality of trenches, the masking layer has a thickness sufficient to both line the trenches with the widths above the threshold size and completely fill the trenches with the widths below the threshold size. A portion of the substrate is exposed at a bottom of the trenches with the widths above the threshold size by etching the masking layer. The plurality of trenches is etched to extend the trenches with the widths above the threshold size to different depths.

    摘要翻译： 用于形成用于半导体器件的隔离沟槽的方法在衬底中形成具有不同宽度的多个沟槽，所述宽度包括高于阈值尺寸的宽度和低于阈值尺寸的宽度。 多个沟槽具有相同的第一深度。 掩蔽层沉积在多个沟槽中，掩模层具有足够的厚度以使沟槽线宽度高于阈值尺寸，并以宽度低于阈值尺寸完全填充沟槽。 通过蚀刻掩模层，将衬底的一部分暴露在沟槽底部，宽度高于阈值大小。 多个沟槽被蚀刻以将具有高于阈值尺寸的宽度的沟槽延伸到不同的深度。