公开(公告)号：US07091103B2

公开(公告)日：2006-08-15

申请号：US10314865

申请日：2002-12-09

申请人： Jochen Beintner ,  Laertis Economikos ,  Michael Wise ,  Andreas Knorr

发明人： Jochen Beintner ,  Laertis Economikos ,  Michael Wise ,  Andreas Knorr

IPC分类号： H01L21/76 ,  H01L21/461 ,  H01L21/302

CPC分类号： H01L21/76819 ,  H01L21/31053 ,  H01L21/31055 ,  H01L27/1087 ,  H01L27/10894

摘要： CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.

摘要翻译： 包含具有沟槽电容器的DRAM阵列的集成电路的CMP用氧化物填充沟槽，导致与周围的支撑结构中的浓度相比密集的氧化物结构的阵列，因此具有更高的负载。 保形层沉积在晶片上，增加阵列中的负载，但填充有效区域之间的空间。 覆盖蚀刻去除阵列和支撑体中的材料。 块蚀刻平衡阵列中的材料和支撑体的数量。 阵列中的补充氧化物沉积将结构之间的空间填充到几乎均匀的密度。

公开(公告)号：US06794242B1

公开(公告)日：2004-09-21

申请号：US09675435

申请日：2000-09-29

申请人： Thomas W. Dyer ,  Andreas Knorr ,  Laertis Economikos ,  Scott Halle ,  Rajeev Malik ,  Norbert Arnod

发明人： Thomas W. Dyer ,  Andreas Knorr ,  Laertis Economikos ,  Scott Halle ,  Rajeev Malik ,  Norbert Arnod

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10891

摘要： A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride remaining in place. Once the devices have been formed and the gate polysilicon has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide fills the regions between and on top of the polysilicon plugs. The Top Oxide is than planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.

摘要翻译： 如在具有垂直堆叠的存取金属氧化物半导体场效应晶体管（MOSFET）的沟槽动态随机存取存储器（DRAM）阵列中，顶部氧化物方法用于在垂直晶体管阵列上形成氧化物层。 顶部氧化物通过首先形成垂直装置而形成，其中衬垫氮化物保持就位。 一旦器件已经形成并且栅极多晶硅已经被平坦化到衬底氮化物的表面之下，衬垫氮化物被剥离掉，留下栅极多晶硅插塞的顶部延伸到活性硅表面之上。 这种多晶硅插塞的图形定义了顶部氧化物沉积的图案。 沉积的顶部氧化物填充多晶硅插塞之间和之上的区域。 顶部氧化物被平坦化回到多晶硅插塞的顶部，因此可以在通过的互连件和垂直装置的栅极之间形成接触。 顶部氧化物层用于将通过的互连与有源硅分离，从而减少两个电平之间的电容耦合，并提供用于后续互连电平的反应离子蚀刻（RIE）图案化的鲁棒蚀刻停止层。

公开(公告)号：US06946345B2

公开(公告)日：2005-09-20

申请号：US10688612

申请日：2003-10-17

申请人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

发明人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

IPC分类号： H01L21/8242 ,  H01L29/94 ,  H01L21/20

CPC分类号： H01L27/10867 ,  H01L27/10864 ,  H01L29/945

摘要： The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

摘要翻译： 本发明提供了一种沟槽存储结构，其包括具有沟槽的衬底，沟槽下部的电容器导体，与电容器导体相邻的沟槽中的导电节点带，电容器导体上方的沟槽顶部氧化物，以及导电 埋在衬底中的邻近沟槽顶部氧化物的衬底。 沟槽顶部氧化物包括导电带上方的掺杂沟槽顶部氧化物层和掺杂沟槽顶部氧化物层上方的未掺杂沟槽顶部氧化物层。

公开(公告)号：US06667504B1

公开(公告)日：2003-12-23

申请号：US10249228

申请日：2003-03-24

申请人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

发明人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

IPC分类号： H01L27108

CPC分类号： H01L27/10867 ,  H01L27/10864 ,  H01L29/945

摘要： The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

摘要翻译： 本发明提供了一种沟槽存储结构，其包括具有沟槽的衬底，沟槽下部的电容器导体，与电容器导体相邻的沟槽中的导电节点带，电容器导体上方的沟槽顶部氧化物，以及导电 埋在衬底中的邻近沟槽顶部氧化物的衬底。 沟槽顶部氧化物包括导电带上方的掺杂沟槽顶部氧化物层和掺杂沟槽顶部氧化物层上方的未掺杂沟槽顶部氧化物层。

公开(公告)号：US06933206B2

公开(公告)日：2005-08-23

申请号：US10683668

申请日：2003-10-10

申请人： Jochen Beintner ,  Andreas Knorr

发明人： Jochen Beintner ,  Andreas Knorr

IPC分类号： H01L21/31 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76229

摘要： An isolation trench formed in a semiconductor substrate and is filled with at least one insulating liner layer that is deposited along sidewalls and a bottom region of the isolation trench and with at least one silicon liner layer that is deposited atop the insulating liner layer. An upper portion of the insulating liner layers are removed, and the silicon liner layers are removed. A remaining portion of the trench is filled with another insulating layer.

摘要翻译： 隔离沟槽，形成在半导体衬底中，并且填充有至少一个绝缘衬层，绝缘衬垫层沿隔离沟槽的侧壁和底部区域沉积，并且至少一层硅衬层沉积在绝缘衬层的顶部。 去除绝缘衬垫层的上部，并去除硅衬层。 沟槽的剩余部分填充有另一绝缘层。

公开(公告)号：US20050079730A1

公开(公告)日：2005-04-14

申请号：US10683668

申请日：2003-10-10

申请人： Jochen Beintner ,  Andreas Knorr

发明人： Jochen Beintner ,  Andreas Knorr

IPC分类号： H01L21/31 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76229

摘要： An isolation trench formed in a semiconductor substrate and is filled with at least one insulating liner layer that is deposited along sidewalls and a bottom region of the isolation trench and with at least one silicon liner layer that is deposited atop the insulating liner layer. An upper portion of the insulating liner layers are removed, and the silicon liner layers are removed. A remaining portion of the trench is filled with another insulating layer.

公开(公告)号：US06566228B1

公开(公告)日：2003-05-20

申请号：US10083744

申请日：2002-02-26

申请人： Jochen Beintner ,  Rama Divakaruni ,  Jack A. Mandelman ,  Andreas Knorr

发明人： Jochen Beintner ,  Rama Divakaruni ,  Jack A. Mandelman ,  Andreas Knorr

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/763 ,  H01L27/1052

摘要： Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

摘要翻译： 公开了一种同时提供用于由衬底材料制成的半导体衬底的阵列和支撑区域的沟槽隔离的方法，所述方法包括提供用于阵列和支撑区域的第一硬掩模层，所述第一硬掩模包括限定沟槽隔离的掩模开口 在阵列和支撑区域中，在阵列区域中提供深阵列沟槽隔离，在足以填充所述掩模开口和深阵列沟槽隔离的支撑和阵列区域上提供覆盖的平面化导电材料层，通过所述第一硬 掩模材料下降到所述半导体衬底中，以便形成支撑沟槽隔离，使得深阵列沟槽隔离和支撑沟槽隔离都具有相同的深度，并且其中包括一定数量的所述导电材料的导电元件保留在 每个所述深阵列沟槽。

公开(公告)号：US06437401B1

公开(公告)日：2002-08-20

申请号：US09824957

申请日：2001-04-03

申请人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

发明人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

IPC分类号： H01L2976

CPC分类号： H01L27/1087 ,  H01L27/10861 ,  H01L27/10864 ,  H01L29/945

摘要： A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.

摘要翻译： 提供了用于改善电荷保留的沟槽电容器结构及其制造方法。 在p型导电性半导体衬底中形成沟槽。 隔离套环位于沟槽的上部。 与沟槽上部相邻的衬底包含第一n +型导电区​​和第二n +型导电区​​。 这些区域各自邻接沟槽的壁并且被p型导电性半导体衬底的一部分垂直分开。 围绕沟槽的周边的空隙形成沟槽的壁，并且位于第一和第二n +型导电区​​域之间的衬底中。

公开(公告)号：US06821865B2

公开(公告)日：2004-11-23

申请号：US10248233

申请日：2002-12-30

申请人： Michael Wise ,  Andreas Knorr

发明人： Michael Wise ,  Andreas Knorr

IPC分类号： H01L21762

CPC分类号： H01L21/76229

摘要： A method of forming deep isolation trenches in the fabrication of ICs is disclosed. The substrate is prepared with deep isolation trenches. The isolation trenches are partially filled with a first dielectric material. An etch mask layer is deposited on the substrate and used to remove excess first dielectric material on the surface of the substrate. The isolation trenches are then completely filled with a second dielectric material. Excess second dielectric material is then removed from the surface of the substrate.

摘要翻译： 公开了一种在IC的制造中形成深隔离沟槽的方法。 用深的隔离沟槽制备衬底。 隔离沟槽部分地填充有第一介电材料。 蚀刻掩模层沉积在衬底上并用于去除衬底表面上的多余的第一介电材料。 隔离沟槽然后用第二电介质材料完全填充。 然后从基板的表面去除过量的第二介电材料。

公开(公告)号：US10189856B2

公开(公告)日：2019-01-29

申请号：US13816020

申请日：2011-05-24

申请人： Claudia Hirth-Dietrich ,  Peter Sandner ,  Johannes-Peter Stasch ,  Andreas Knorr ,  Georges Von Degenfeld ,  Michael Hahn ,  Markus Follmann

发明人： Claudia Hirth-Dietrich ,  Peter Sandner ,  Johannes-Peter Stasch ,  Andreas Knorr ,  Georges Von Degenfeld ,  Michael Hahn ,  Markus Follmann

IPC分类号： A61K31/437 ,  A61K31/197 ,  A61K31/427 ,  A61K31/4439 ,  A61K31/506 ,  A61K31/519 ,  A61K31/5377 ,  A61K45/06 ,  C07D495/04 ,  C07D471/04 ,  A61K31/426 ,  C07C229/38 ,  C07D261/10 ,  C07D277/30 ,  C07D333/34 ,  C07D401/04 ,  C07D417/06 ,  C07D487/04

摘要： The use of sGC stimulators, sGC activators alone, or in combination with PDE5 inhibitors for the prevention and treatment of fibrotic diseases, such as systemic sclerosis, scleroderma, and the concomitant fibrosis of internal organs.