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    Method of forming suspended transmission line structures in back end of line processing
    52.
    发明授权
    Method of forming suspended transmission line structures in back end of line processing 失效
    在线路处理后端形成悬挂传输线结构的方法

    公开(公告)号：US07005371B2

    公开(公告)日：2006-02-28

    申请号：US10709357

    申请日：2004-04-29

    申请人： Anil K. Chinthakindi ,  Robert A. Groves ,  Youri V. Tretiakov ,  Kunal Vaed ,  Richard P. Volant

    发明人： Anil K. Chinthakindi ,  Robert A. Groves ,  Youri V. Tretiakov ,  Kunal Vaed ,  Richard P. Volant

    IPC分类号： H01L21/4763

    CPC分类号： H01P11/003 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/53238 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

    摘要翻译： 用于形成用于半导体器件的传输线结构的方法包括在第一金属化层上形成层间电介质层，去除层间电介质层的一部分，并在通过去除部分的部分产生的一个或多个空隙内形成牺牲材料 层间电介质层。 信号传输线形成在层间电介质层上形成的第二金属化层，信号传输线设置在牺牲材料之上。 包括在第二金属化水平内的电介质材料的一部分被去除以暴露牺牲材料，其中牺牲材料的一部分通过穿过信号传输线形成的多个访问孔而露出。 去除牺牲材料，以在信号传输线下方产生气隙。

    Method of fabrication of thin film resistor with zero TCR
    53.
    发明授权
    Method of fabrication of thin film resistor with zero TCR 有权
    具有零TCR的薄膜电阻器的制造方法

    公开(公告)号：US06890810B2

    公开(公告)日：2005-05-10

    申请号：US10727946

    申请日：2003-12-04

    申请人： Jeffrey R. Amadon ,  Anil K. Chinthakindi ,  Kenneth J. Stein ,  Kwong H. Wong

    发明人： Jeffrey R. Amadon ,  Anil K. Chinthakindi ,  Kenneth J. Stein ,  Kwong H. Wong

    IPC分类号： H01C7/00 ,  H01C7/06 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01C7/06 ,  H01C7/006

    摘要： A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/° C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).

    摘要翻译： 提供具有基本为零TCR的薄膜电阻器及其制造方法。 薄膜电阻器包括彼此位于的至少两个电阻材料。 每个电阻器材料具有不同的电阻率温度系数，使得薄膜电阻器的电阻率的有效温度系数基本上为0ppm /℃。薄膜电阻器可以集成到互连结构中，或者可以与金属 - 绝缘体 - 金属电容器（MIMCAP）。

    On-chip decoupling capacitor structures
    54.
    发明授权
    On-chip decoupling capacitor structures 有权
    片上去耦电容结构

    公开(公告)号：US07968929B2

    公开(公告)日：2011-06-28

    申请号：US11834961

    申请日：2007-08-07

    申请人： Anil K. Chinthakindi ,  Eric Thompson

    发明人： Anil K. Chinthakindi ,  Eric Thompson

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L29/945 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.

    摘要翻译： 本公开提供了片上去耦电容器结构，其具有与形成在后端线路布线中的无源电容集成的沟槽电容器，以提供改进的总电容密度。 在一些实施例中，该结构包括至少一个深沟槽电容器和形成在至少两个后端线路布线层中的无源电容器。 沟槽和无源电容器通过其中一个布线层进行电连接。 在其它实施例中，该结构包括至少一个深沟槽电容器，第一后端线路接线电平和第二后端线路布线电平。 具有电介质的深沟槽电容器，其具有终止于浅沟槽隔离区域的下表面处的上边缘。 第一布线电平与沟槽电容器电连通。 第二布线电平通过垂直连接器垂直电连接到第一布线层，以便形成无源电容器。

    Integrated BEOL Thin Film Resistor
    55.
    发明申请
    Integrated BEOL Thin Film Resistor 有权
    集成BEOL薄膜电阻器

    公开(公告)号：US20110127635A1

    公开(公告)日：2011-06-02

    申请号：US13023579

    申请日：2011-02-09

    申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L23/58

    CPC分类号： H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

    摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。

    High capacitance density vertical natural capacitors
    57.
    发明授权
    High capacitance density vertical natural capacitors 有权
    高电容密度垂直天然电容

    公开(公告)号：US07866015B2

    公开(公告)日：2011-01-11

    申请号：US12194564

    申请日：2008-08-20

    申请人： Anil K. Chinthakindi

    发明人： Anil K. Chinthakindi

    IPC分类号： H01G9/00 ,  H01G7/00

    CPC分类号： H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T29/417 ,  Y10T29/435 ,  H01L2924/00

    摘要： Disclosed are embodiments of a method of forming a capacitor with inter-digitated vertical plates such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.

    摘要翻译： 公开了一种形成具有数字化的垂直板的电容器的方法的实施例，使得板之间的有效间隙距离减小。 该间隙宽度减小显着增加了电容器的电容密度。 通过用节点掩蔽连接点，通过从垂直板之间蚀刻电介质材料，并通过从垂直板下方蚀刻牺牲材料，在线加工的后端完成间隙宽度减小。 介电材料的蚀刻形成空气间隙，一旦去除了牺牲材料，就可以使用各种技术使板在这些气隙上塌陷。 可以通过沉积第二电介质材料（例如，高k电介质）来填充任何剩余的空气间隙，这将进一步增加电容密度并将封装电容器，以便使垂直板之间的距离减小。

    On-chip decoupling capacitor structures
    59.
    发明授权
    On-chip decoupling capacitor structures 有权
    片上去耦电容结构

    公开(公告)号：US07816762B2

    公开(公告)日：2010-10-19

    申请号：US11834956

    申请日：2007-08-07

    申请人： Anil K. Chinthakindi ,  Eric Thompson

    发明人： Anil K. Chinthakindi ,  Eric Thompson

    IPC分类号： H01L29/00

    CPC分类号： H01L29/945 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with planar capacitors to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor, at least one planar capacitor, and a metal layer interconnecting said deep trench and planar capacitors. In other embodiments, the structure includes at least one deep trench capacitor and a metal layer in electrical communication with the at least one deep trench capacitor. The at least one deep trench capacitor has a shallow trench isolation region, a doped region, an inner electrode, and a dielectric between the doped region and the inner electrode. The dielectric has an upper edge that terminates at a lower surface of the shallow trench isolation region.

    摘要翻译： 本公开提供具有与平面电容器集成的沟槽电容器的片上去耦电容器结构，以提供改进的总电容密度。 在一些实施例中，该结构包括至少一个深沟槽电容器，至少一个平面电容器和互连所述深沟槽和平面电容器的金属层。 在其他实施例中，该结构包括至少一个深沟槽电容器和与至少一个深沟槽电容器电连通的金属层。 所述至少一个深沟槽电容器在所述掺杂区域和所述内部电极之间具有浅沟槽隔离区域，掺杂区域，内部电极和电介质。 电介质具有终止在浅沟槽隔离区的下表面处的上边缘。

    Polysilicon containing resistor with enhanced sheet resistance precision and method for fabrication thereof
    60.
    发明授权
    Polysilicon containing resistor with enhanced sheet resistance precision and method for fabrication thereof 失效
    具有增强的薄层电阻精度的含多晶硅的电阻器及其制造方法

    公开(公告)号：US07691717B2

    公开(公告)日：2010-04-06

    申请号：US11458494

    申请日：2006-07-19

    申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

    发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

    IPC分类号： H01L21/20

    CPC分类号： H01L27/0802 ,  H01L21/26513 ,  H01L28/20

    摘要： A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.

    摘要翻译： 含多晶硅的电阻器包括：（1）选自硼和二氟化硼的p掺杂剂; 和（2）选自砷和磷的n掺杂剂。 p掺杂剂和n掺杂剂中的每一个掺杂剂的掺杂剂浓度从每立方厘米约1e18至约1e21掺杂剂原子。 用于形成多晶硅电阻器的方法使用相对于每平方厘米约1e14至约1e16掺杂剂离子的注入剂量。 p掺杂剂和n掺杂剂可以同时或顺序地提供。 对于具有约100至约5000欧姆/平方的薄层电阻的多晶硅电阻器，该方法提供某些多晶硅电阻器的薄层电阻百分比标准偏差小于约1.5％。