公开(公告)号：US08397191B1

公开(公告)日：2013-03-12

申请号：US13290903

申请日：2011-11-07

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G06F17/50 ,  G06F11/00 ,  G01V3/00 ,  G01V7/00 ,  G01R31/28

CPC分类号： G06F17/5054 ,  G06F17/5081

摘要： In one embodiment, a method is provided for determining a level of resilience of a circuit to single event upsets based on a layout of a circuit design. A set of locations in the layout of the circuit design is selected. A respective maximum level of linear energy transfer (LET) that is tolerable for each location in the selected set is determined. For each determined maximum level of LET, cross-section values at locations having the maximum level of LET are summed to determine a respective total cross-section value for the maximum level of LET. For each determined maximum level of LET, the total cross-section value is divided by the determined maximum level of LET to produce respective intermediate values. The respective intermediate values are summed to determine a level of resilience.

摘要翻译： 在一个实施例中，提供了一种用于基于电路设计的布局来确定电路对单事件不匹配的弹性水平的方法。 选择电路设计布局中的一组位置。 确定对所选集合中的每个位置可容忍的相应的最大线性能量传递（LET）。 对于每个确定的LET的最大水平，将具有最大水平LET的位置处的横截面值相加以确定LET的最大水平的相应总横截面值。 对于每个确定的最大水平的LET，将总截面值除以确定的LET的最大水平以产生相应的中间值。 相应的中间值相加以确定弹性水平。

公开(公告)号：US08386990B1

公开(公告)日：2013-02-26

申请号：US12961753

申请日：2010-12-07

申请人： Stephen M. Trimberger ,  Austin H. Lesea

发明人： Stephen M. Trimberger ,  Austin H. Lesea

IPC分类号： G06F17/50 ,  G06F19/00 ,  H01L23/58 ,  H01L25/00 ,  H03K19/00

CPC分类号： G06F21/73 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention relates to an integrated circuit such as an FPGA wherein a stable unique identifier is produced by reading an intrinsic characteristic of the IC such as a physically unclonable function, and a related method. In one embodiment, a first unique identifier is generated using the intrinsic characteristic and is subdivided into a plurality of first subsets. A second unique identifier is received and subdivided into a plurality of second subsets. The first and second subsets are compared to identify matching subsets to generate the stable unique identifier. Each of the one or more matching subsets includes a particular one of the plurality of first subsets that matches a corresponding one of the plurality of second subsets. The stable unique identifier can be integrated into logic of the IC. Prior to comparing the subsets, the first and second subsets can be transformed with one-way functions.

摘要翻译： 本发明的实施例涉及诸如FPGA的集成电路，其中通过读取诸如物理不可克隆功能的IC的固有特性来产生稳定的唯一标识符，以及相关方法。 在一个实施例中，使用本征特征生成第一唯一标识符，并将其细分为多个第一子集。 接收第二唯一标识符并将其细分成多个第二子集。 比较第一和第二子集以识别匹配子集以产生稳定的唯一标识符。 所述一个或多个匹配子集中的每一个包括与所述多个第二子集中的相应一个匹配的所述多个第一子集中的特定一个子集。 稳定的唯一标识符可以集成到IC的逻辑中。 在比较子集之前，第一和第二子集可以用单向函数进行变换。

公开(公告)号：US08117497B1

公开(公告)日：2012-02-14

申请号：US12247916

申请日：2008-11-17

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G06F11/00

CPC分类号： G06F11/10

摘要： A method and apparatus for the detection and correction of soft errors existing within an integrated circuit (IC). Run-time check stops are utilized in conjunction with processor-based, hardware mechanisms to detect and correct soft errors. At run-time, each check stop facilitates a snap shot of the hardware and/or software state of the IC to be stored into hardware and/or software based memory. Should a soft error be detected, execution is halted and the executable state of the IC that conforms to a previous check-stop location may be re-established after the soft error(s) are optionally corrected. In alternate embodiments, hardware based mechanisms may be exclusively utilized to both detect and correct the soft errors.

摘要翻译： 用于检测和校正存在于集成电路（IC）内的软错误的方法和装置。 运行时检查停止与基于处理器的硬件机制结合使用，以检测和纠正软错误。 在运行时，每个检查停止便于将要存储到硬件和/或基于软件的存储器中的IC的硬件和/或软件状态的快照。 如果检测到软错误，执行停止，并且可以在可选地校正软错误之后重新建立符合先前检查停止位置的IC的可执行状态。 在替代实施例中，基于硬件的机制可以专门用于检测和校正软错误。

公开(公告)号：US07944769B1

公开(公告)日：2011-05-17

申请号：US12579274

申请日：2009-10-14

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G11C5/14

CPC分类号： H03K3/02335

摘要： A system for detecting power-on of a circuit block within an integrated circuit (IC). The system can include a latch including a latch output and an inverted latch output. The latch can be coupled to, and powered by, a power supply providing power to the circuit block within the IC. The system further can include an exclusive OR circuit. The exclusive OR circuit can include an input stage coupled to the latch output and the inverted latch output. The exclusive OR circuit generates an output signal indicating whether the circuit block is in a power-on state.

摘要翻译： 一种用于检测集成电路（IC）内的电路块的通电的系统。 该系统可以包括具有锁存器输出和反相锁存器输出的锁存器。 锁存器可以耦合到由IC提供电力的电源并由其供电，该电源为IC内的电路块提供电力。 系统还可以包括异或电路。 异或电路可以包括耦合到锁存器输出和反相锁存器输出的输入级。 异或电路产生指示电路块是否处于通电状态的输出信号。

公开(公告)号：US07739565B1

公开(公告)日：2010-06-15

申请号：US11880362

申请日：2007-07-19

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G01R31/28 ,  H03K17/693

CPC分类号： G06F11/1004

摘要： A programmable logic device includes a configuration memory, a checker, and a redundant-logic detector. An array of programmable logic and interconnect resources is configurable to implement a selected user design. The configuration memory stores configuration data that configures the array of programmable logic and interconnect resources to implement the specified user design. A checker calculates a sequence of checksums from the configuration data that is stored in the configuration memory. A redundant-logic detector indicates corruption of the configuration data stored in the configuration memory in response to at least two consecutive checksums in the sequence not matching a reference value.

摘要翻译： 可编程逻辑器件包括配置存储器，检验器和冗余逻辑检测器。 一组可编程逻辑和互连资源可配置为实现选定的用户设计。 配置存储器存储配置可编程逻辑阵列和互连资源的配置数据，以实现指定的用户设计。 检查器根据存储在配置存储器中的配置数据计算一系列校验和。 响应于不匹配参考值的序列中的至少两个连续校验和，冗余逻辑检测器指示存储在配置存储器中的配置数据的损坏。

公开(公告)号：US07403051B1

公开(公告)日：2008-07-22

申请号：US11340389

申请日：2006-01-26

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： H03L7/00 ,  H03K5/153 ,  H03K5/22

CPC分类号： H03K19/17772 ,  G01R19/16552 ,  H03K17/22

摘要： Determining voltage level validity for a power-on reset condition is described. A supply voltage is applied to an integrated circuit. An oscillating signal is generated responsive to the supply voltage applied. A counting occurs responsive to oscillations of the oscillating signal. A triggering occurs responsive to reaching a first voltage level of the supply voltage for the power-on reset condition. A first count of the counting occurs responsive to the triggering. A second count is selected responsive to the first count. A second level is accepted as having at least met a threshold for the supply voltage responsive to the counting reaching the second count for the power-on reset condition.

摘要翻译： 对上电复位条件确定电压电平有效性进行说明。 电源电压被施加到集成电路。 响应于施加的电源电压产生振荡信号。 响应于振荡信号的振荡进行计数。 响应于达到上电复位条件的电源电压的第一电压电平而发生触发。 响应于触发，计数的第一个计数发生。 响应于第一计数选择第二计数。 第二级被接受为响应于计数达到上电复位条件的第二计数，至少满足电源电压的阈值。

公开(公告)号：US07142823B1

公开(公告)日：2006-11-28

申请号：US10769205

申请日：2004-01-29

申请人： John D. Logue ,  Austin H. Lesea ,  Wei Lu

发明人： John D. Logue ,  Austin H. Lesea ,  Wei Lu

IPC分类号： H04B1/40

CPC分类号： H03L7/0996 ,  H03L7/085

摘要： A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein a rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates an error value based on the snapshots. The tapped delay line module produces the output clock based on the error value.

摘要翻译： 低抖动数字频率合成器包括第一计数器模块，第二计数器模块，快照模块，误差值生成模块和抽头延迟线。 第一计数器模块计算输入时钟的M个周期的间隔以产生第一计数。 第二计数器模块计算输出时钟的D个周期的间隔以产生第二计数，其中输出时钟的速率对应于输入时钟的速率的M / D倍。 快照模块定期拍摄第一和第二个计数的快照，以生成快照。 错误值生成模块根据快照生成错误值。 抽头延迟线模块根据误差值产生输出时钟。

公开(公告)号：US06963218B1

公开(公告)日：2005-11-08

申请号：US10215924

申请日：2002-08-09

申请人： Mark A. Alexander ,  Austin H. Lesea

发明人： Mark A. Alexander ,  Austin H. Lesea

IPC分类号： H03K17/16 ,  H03K19/00 ,  H03K19/0185 ,  H04L5/16 ,  H04L25/02

CPC分类号： H04L5/16 ,  H03K17/167 ,  H03K19/0005 ,  H03K19/018592 ,  H04L25/0278

摘要： Method and apparatus for a bi-direction interface and communication link are described. More particularly, an input/output block is formed with a digitally controlled impedance output driver output coupled at an input/output node to an input terminal of a differential amplifier. Another terminal of the differential amplifier is used for inputting a reference voltage. As the digitally controlled impedance output buffer may be adjusted for impedance matching with transmission line impedance, no parallel terminating resistance is needed. Accordingly, two such input/output blocks may be coupled to form a bi-directional communication link with the advantage of an absence of parallel termination resistance at inputs to such input/output blocks.

摘要翻译： 描述了用于双向接口和通信链路的方法和装置。 更具体地，输入/输出块形成有数字控制的阻抗输出驱动器输出，其在输入/输出节点耦合到差分放大器的输入端。 差分放大器的另一个端子用于输入参考电压。 由于数字控制的阻抗输出缓冲器可能被调整以用于与传输线路阻抗的阻抗匹配，因此不需要并联终端电阻。 因此，可以将两个这样的输入/输出块耦合以形成双向通信链路，其优点在于在这种输入/输出块的输入处不存在并行终端电阻。

公开(公告)号：US06542040B1

公开(公告)日：2003-04-01

申请号：US09994524

申请日：2001-11-26

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： H03B2700

CPC分类号： H03L7/107 ,  H03L7/087 ,  H03L7/093 ,  H03L7/0997 ,  H03L7/18

摘要： A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop filter is small. The PLL includes a first phase detector, a second phase detector, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. In a first step, oscillator output is fed back via the loop divider to the first phase detector. Oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a phase lock step. The programmable loop filter is controlled to realize the selected loop filter and the selected loop filter is switched into a control loop involving the second phase detector. The control loop controls the oscillator to achieve phase lock by varying a supply voltage supplied to the oscillator.

公开(公告)号：US06525560B1

公开(公告)日：2003-02-25

申请号：US10017516

申请日：2001-12-12

申请人： Stephen M. Trimberger ,  Austin H. Lesea

发明人： Stephen M. Trimberger ,  Austin H. Lesea

IPC分类号： H03K19173

CPC分类号： H03K19/17748

摘要： A programmable logic device (PLD) includes a die having first and second bond pads, each being weakly pulled to a first voltage. A package enclosing the die has an external pad configured to receive a second voltage. A conductor couples one and only one of the first and second bond pads to the external pad, such that one bond pad is pulled to the first voltage, and the other bond pad is pulled to the second voltage. A logic circuit on the die is coupled the first and second bond pads. The logic circuit enables the PLD to be configured in response to a first type of bit stream if the first bond pad is pulled to the second voltage, and enables the PLD to be configured only in response to a second type of bit stream if the second bond pad is pulled to the second voltage. In another embodiment, a bond pad is weakly pulled to a first voltage, and can be connected or not connected to an external pin for applying a second voltage.

摘要翻译： 可编程逻辑器件（PLD）包括具有第一和第二接合焊盘的管芯，每个引脚被弱拉至第一电压。 封装芯片的封装具有被配置为接收第二电压的外部焊盘。 导体将第一和第二接合焊盘中的一个并且仅一个耦合到外部焊盘，使得一个焊盘被拉到第一电压，而另一个焊盘被拉到第二电压。 芯片上的逻辑电路耦合第一和第二接合焊盘。 如果第一接合焊盘被拉到第二电压，则逻辑电路使得能够响应于第一类型的位流来配置PLD，并且使得仅当响应于第二类型的位流而配置PLD时 接合焊盘被拉到第二电压。 在另一个实施例中，接合焊盘被弱拉至第一电压，并且可以连接或不连接到用于施加第二电压的外部引脚。