公开(公告)号：US07142823B1

公开(公告)日：2006-11-28

申请号：US10769205

申请日：2004-01-29

申请人： John D. Logue ,  Austin H. Lesea ,  Wei Lu

发明人： John D. Logue ,  Austin H. Lesea ,  Wei Lu

IPC分类号： H04B1/40

CPC分类号： H03L7/0996 ,  H03L7/085

摘要： A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein a rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates an error value based on the snapshots. The tapped delay line module produces the output clock based on the error value.

摘要翻译： 低抖动数字频率合成器包括第一计数器模块，第二计数器模块，快照模块，误差值生成模块和抽头延迟线。 第一计数器模块计算输入时钟的M个周期的间隔以产生第一计数。 第二计数器模块计算输出时钟的D个周期的间隔以产生第二计数，其中输出时钟的速率对应于输入时钟的速率的M / D倍。 快照模块定期拍摄第一和第二个计数的快照，以生成快照。 错误值生成模块根据快照生成错误值。 抽头延迟线模块根据误差值产生输出时钟。

公开(公告)号：US06737925B1

公开(公告)日：2004-05-18

申请号：US10253275

申请日：2002-09-24

申请人： John D. Logue ,  Andrew R. Percey ,  Austin H. Lesea

发明人： John D. Logue ,  Andrew R. Percey ,  Austin H. Lesea

IPC分类号： G11C700

CPC分类号： H03L7/00

摘要： Method and apparatus for providing a controlled voltage to an integrated circuit is described. A first frequency value indicative of a first voltage is compared to a second frequency value indicative of a second voltage. The second frequency value is adjusted by the second voltage until the second frequency value is within a range of the first frequency value. Additionally, the second voltage may be adjusted to maintain the second frequency value within the range.

摘要翻译： 描述了向集成电路提供受控电压的方法和装置。 将表示第一电压的第一频率值与表示第二电压的第二频率值进行比较。 第二频率值由第二电压调节，直到第二频率值在第一频率值的范围内。 另外，可以调整第二电压以将第二频率值保持在该范围内。

公开(公告)号：US07619486B1

公开(公告)日：2009-11-17

申请号：US11715534

申请日：2007-03-07

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： H03L1/04

CPC分类号： H03L1/022 ,  G01K7/346 ,  H03L1/026 ,  H03L7/18

摘要： An integrated circuit fabricated in a multiple oxide process can be used to provide a temperature-insensitive circuit. The temperature-insensitive circuit can be a ring oscillator; this ring oscillator can be used as a low-cost integrated reference frequency to monitor and to modify the behavior of the integrated to produce the desired results. In some embodiments, the reference oscillator output can be compared to second oscillator output where the second oscillator performance is temperature-sensitive. The comparison result can be monitored and processed to power down the integrated circuit.

摘要翻译： 可以使用以多重氧化物工艺制造的集成电路来提供温度不敏感的电路。 温度不敏感电路可以是环形振荡器; 该环形振荡器可以用作低成本的集成参考频率来监视和修改集成的行为以产生期望的结果。 在一些实施例中，可以将参考振荡器输出与第二振荡器输出进行比较，其中第二振荡器性能是温度敏感的。 可以对比较结果进行监控和处理，以使集成电路断电。

公开(公告)号：US07254157B1

公开(公告)日：2007-08-07

申请号：US10109130

申请日：2002-03-27

申请人： Patrick J. Crotty ,  Austin H. Lesea

发明人： Patrick J. Crotty ,  Austin H. Lesea

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713

CPC分类号： H03K3/84

摘要： A method of and apparatus for generating a spread spectrum clock signal on an integrated circuit are provided. A target frequency generated by a ring oscillator can be modulated by varying a supply voltage to the ring oscillator, thereby changing the target frequency. In one embodiment, the supply voltage is generated by an analog multiplexer that can be digitally controlled. A fixed voltage source can provide an input signal to the analog multiplexer. In one embodiment, the fixed voltage source can be implemented with a unity gain amplifier.

摘要翻译： 提供了一种在集成电路上产生扩频时钟信号的方法和装置。 可以通过改变环形振荡器的电源电压来调制由环形振荡器产生的目标频率，从而改变目标频率。 在一个实施例中，电源电压由可被数字控制的模拟多路复用器产生。 固定电压源可以向模拟多路复用器提供输入信号。 在一个实施例中，固定电压源可以用单位增益放大器来实现。

公开(公告)号：US07240320B1

公开(公告)日：2007-07-03

申请号：US10989679

申请日：2004-11-16

申请人： Stephen M. Trimberger ,  Austin H. Lesea ,  Bernard J. New

发明人： Stephen M. Trimberger ,  Austin H. Lesea ,  Bernard J. New

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A method of implementing a design on a programmable logic device (PLD) includes generating a database that identifies correspondence between resources and programming frames of the PLD. A first PLD design is compiled, wherein the first design uses a first set of resources in a first manner. Costs associated with using the first set of resources of the first design in the first manner are reduced. A second PLD design is then compiled, applying the reduced costs associated with using the first set of resources. A second set of resources required to compile the second design is identified, wherein the second set of resources is not used in the same manner as the first set of resources. A set of programming frames associated with the second set of resources is identified. Costs associated with using a third set of resources associated with the set of programming frames are increased.

摘要翻译： 在可编程逻辑器件（PLD）上实现设计的方法包括生成识别PLD的资源和编程帧之间的对应关系的数据库。 编译第一PLD设计，其​​中第一设计以第一方式使用第一组资源。 降低了以第一种方式使用第一种设计的第一组资源相关联的成本。 然后编制第二PLD设计，应用与使用第一组资源相关联的降低的成本。 识别编译第二设计所需的第二组资源，其中第二组资源不以与第一组资源相同的方式使用。 识别与第二组资源相关联的一组编程帧。 与使用与该组编程帧相关联的第三组资源相关联的成本增加。

公开(公告)号：US07062692B1

公开(公告)日：2006-06-13

申请号：US10255502

申请日：2002-09-26

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/31726

摘要： Method and apparatus are described for duty cycle determination and adjustment. More particularly, an output signal is sampled and provided to duty cycle check circuitry which characterizes the duty cycle of the sampled output signal. This characterization may be provided to a wafer prober or integrated circuit tester to determine whether duty cycle is within an acceptance range. Alternatively, the duty cycle indicator signal may be provided to drive adjustment circuitry. In response to duty cycle not being within an acceptance range, drive adjust circuitry provides a drive adjustment signal to adjust duty cycle at an output buffer by turning on one or more p-channel drive transistors, one or more n-channel drive transistors, or a combination of both. Moreover, wells may be biased responsive to a detected duty cycle in order to correct the duty cycle.

摘要翻译： 描述了用于占空比确定和调整的方法和装置。 更具体地，输出信号被采样并提供给表征采样输出信号的占空比的占空比检查电路。 该表征可以提供给晶片探测器或集成电路测试器，以确定占空比是否在接受范围内。 或者，占空比指示信号可以被提供给驱动调整电路。 响应于占空比不在允许范围内，驱动调节电路提供驱动调节信号，以通过接通一个或多个p沟道驱动晶体管，一个或多个n沟道驱动晶体管或 两者的结合。 此外，孔可以响应于检测到的占空比而被偏置，以便校正占空比。

公开(公告)号：US06849951B1

公开(公告)日：2005-02-01

申请号：US10377863

申请日：2003-02-28

申请人： Stephen M. Trimberger ,  Austin H. Lesea

发明人： Stephen M. Trimberger ,  Austin H. Lesea

IPC分类号： H01L23/528 ,  H01L23/64 ,  H01L25/065 ,  H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/642 ,  H01L24/48 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/16152 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A die having a bypass capacitor is stacked on another die having an active circuit. The active circuit draws a spike of current, for example, during a switching period of a voltage on its output lead from one digital logic level to another digital logic level. The bypass capacitor provides a portion of the spike of current through a conductive plug that extends from a plate of the bypass capacitor to a power lead of the active circuit. The length of the conductive plug is reduced by extending the conductive plug from the bypass capacitor to the active circuit orthogonally to the planar orientation of the dice. Reducing the length of the conductive plug reduces the resistance and inductance of the conductive plug and, in turn, reduces the drop in voltage between the voltage on the bypass capacitor and the voltage on the power lead of the active circuit.

摘要翻译： 具有旁路电容器的管芯堆叠在具有有源电路的另一管芯上。 有源电路例如在其输出引线上的电压从一个数字逻辑电平到另一数字逻辑电平的开关周期期间画出电流尖峰。 旁路电容器通过从旁路电容器的板延伸到有源电路的电源线的导电插头提供电流尖峰的一部分。 通过将导电插塞从旁路电容器延伸到与裸片的平面取向正交的有源电路，导电插头的长度减小。 降低导电插头的长度会降低导电插头的电阻和电感，进而降低旁路电容器上的电压与有源电路的电源线上的电压之间的电压降。

公开(公告)号：US06735110B1

公开(公告)日：2004-05-11

申请号：US10125666

申请日：2002-04-17

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G11C1100

CPC分类号： G11C11/4125

摘要： Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

公开(公告)号：US06445238B1

公开(公告)日：2002-09-03

申请号：US09452234

申请日：1999-12-01

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： H03H1126

CPC分类号： H03H11/265 ,  H03K2005/00143

摘要： The supply voltage to which a delay circuit's buffer stages are coupled is adjusted in response to changes in temperature according to a predetermined relationship to maintain a substantially constant buffer stage gate delay over temperature variations. Decreasing gate delays resulting from decreases in temperature are offset by decreasing the supply voltage, which in turn increases gate delays. Conversely, increasing gate delays resulting from increases in temperature are offset by increasing the supply voltage, which in turn decreases gate delays. In some embodiments, a control circuit is connected to the reference voltage circuit that supplies VCC to the delay circuit, and adjusts VCC in response to temperature to maintain substantially constant gate delay over temperature. In one embodiment, the control circuit includes a microprocessor and a look-up table containing desired supply voltage versus temperature mappings. In another embodiment, the control circuit is formed as part of an existing bandgap reference circuit associated with the reference voltage circuit, and therefore consumes minimal silicon area.

摘要翻译： 响应于根据预定关系的温度变化来调节延迟电路的缓冲级耦合到的电源电压，以保持在温度变化上基本恒定的缓冲级门延迟。 通过降低电源电压来抵消由温度降低导致的门延迟的降低，这进而增加了门延迟。 相反，由于温度升高引起的栅极延迟增加可通过增加电源电压来抵消，这进而降低了栅极延迟。 在一些实施例中，控制电路连接到将VCC提供给延迟电路的参考电压电路，并且响应于温度来调节VCC以在温度上保持基本恒定的门延迟。 在一个实施例中，控制电路包括微处理器和包含期望的电源电压对温度映射的查找表。 在另一个实施例中，控制电路形成为与参考电压电路相关联的现有带隙参考电路的一部分，因此消耗最小的硅面积。

公开(公告)号：US06351145B1

公开(公告)日：2002-02-26

申请号：US09827615

申请日：2001-04-06

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： H03K19177

CPC分类号： H03M1/004 ,  H03M1/365 ,  H03M1/46

摘要： An analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry. In a digital application, a comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage. Adjusting of the reference voltage allows the interface cell to support different digital I/O standards. In one embodiment, the comparator is not used for this digital purpose, but rather is used as a comparator in an ADC. A flash ADC is realized by using the comparators of numerous interface cells as the comparators of the flash ADC. Conversion speed is increased by reducing the impedance of the analog signal input path. An on-chip resistor string is provided so that the flash ADC can be realized without external components. In another embodiment, the comparator of the interface cell is the comparator of a successive approximation ADC. In some embodiments, an interface cell has a pad that is usable for receiving a digital signal or for receiving an analog signal. The interface cell includes special dedicated analog circuitry that has a differential input lead that is programmably couplable to the pad.

摘要翻译： 模数转换器（ADC）在现场可编程门阵列（FPGA）中实现，而无需添加特殊的专用模拟电路。 在数字应用中，FPGA的接口单元中的比较器将输入的数字信号与参考电压进行比较。 调整参考电压允许接口单元支持不同的数字I / O标准。 在一个实施例中，比较器不用于该数字目的，而是用作ADC中的比较器。 闪存ADC通过使用大量接口单元的比较器作为闪存ADC的比较器来实现。 通过降低模拟信号输入路径的阻抗来提高转换速度。 提供片上电阻串，使闪存ADC无需外部元件即可实现。 在另一个实施例中，接口单元的比较器是逐次逼近ADC的比较器。 在一些实施例中，接口单元具有可用于接收数字信号或用于接收模拟信号的焊盘。 接口单元包括专用的专用模拟电路，其具有可编程地耦合到焊盘的差分输入引线。