公开(公告)号：US20200303420A1

公开(公告)日：2020-09-24

申请号：US16610673

申请日：2019-05-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping LONG

IPC: H01L27/12

Abstract: An array substrate includes: a base substrate; one or more first signal lines provided on the base substrate; a plurality of repair line sets also provided on the base substrate and configured to repair the first signal lines, each of the repair line sets comprising one or more repair lines which intersect with and are insulated from at least one of the first signal lines; and one or more second signal lines also provided on the base substrate, at least one of the one or more second signal lines having one end which is arranged to intersect with and be insulated from the one or more repair lines, and the other end which is connected to a driving circuit for supplying an electrical signal to the one or more first signal lines. The second signal line is different from the first signal line.

公开(公告)号：US20200026136A1

公开(公告)日：2020-01-23

申请号：US16476191

申请日：2018-10-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping LONG ,  Yong QIAO ,  Xinyin WU

IPC: G02F1/1362 ,  G02F1/1345

Abstract: The present disclosure provides an array substrate and a display panel, where the array substrate includes: a plurality of pixel structures, each of the pixel structures comprises at least one pixel region, wherein a signal wire is provided at a side of the pixel region, and a pixel electrode is provided in the pixel region, a shield electrode being in a same layer as the pixel electrode is provided at a side of the pixel electrode proximal to the signal wire, and the shield electrode is electrically coupled to a common electrode line. The technical solution of the present disclosure can improve the chaos in electric field at the edge of the area of the pixel region between the pixel electrode and the signal wire, and it is beneficial to reduce light leakage and increase the aperture ratio.

公开(公告)号：US20180294556A1

公开(公告)日：2018-10-11

申请号：US15864306

申请日：2018-01-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yongchun LU ,  Xinyin WU ,  Hongfei CHENG ,  Chunping LONG

IPC: H01Q1/36 ,  H01Q3/26

Abstract: An antenna structure, a manufacturing method thereof, and a communication device are disclosed. The antenna structure includes a first substrate, a second substrate, a dielectric layer, a plurality of first electrodes and a plurality of second electrodes. The dielectric layer is disposed between the first substrate and the second substrate; the plurality of first electrodes are disposed at intervals on a side of the first substrate adjacent to the dielectric layer; the plurality of second electrodes are disposed at intervals on a side of the second substrate adjacent to the dielectric layer; a side of the first substrate facing the second substrate includes a plurality of first recess portions each including a first concaved surface which is dented into the first substrate; the dielectric layer is at least partly disposed in the plurality of first recess portions.

公开(公告)号：US20180061339A1

公开(公告)日：2018-03-01

申请号：US15526441

申请日：2016-05-06

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping LONG ,  Yong QIAO

IPC: G09G3/36 ,  G09G3/20

Abstract: Exemplary embodiments of the present disclosure provide a demultiplexer circuit, a signal line circuit and a corresponding output circuit, and a display. The demultiplexer circuit includes at least one first input terminal configured to receive a first signal, at least one second input terminal configured to receive a second signal, at least one first output terminal configured to output the first signal and the second signal, and at least one second output terminal configured to output the first signal and the second signal. The demultiplexer circuit according to exemplary embodiments of the present disclosure can reduce the signal input lines and the input ports, further facilitate to reduce the layout space of wiring.

公开(公告)号：US20180033806A1

公开(公告)日：2018-02-01

申请号：US15660999

申请日：2017-07-27

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping LONG ,  Hongfei CHENG

IPC: H01L27/12 ,  H01L27/02

CPC classification number: H01L27/1244 ,  H01L27/0266 ,  H01L27/0296 ,  H01L27/124

Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes a plurality of signal lines, a plurality of secondary discharging lines arranged substantially parallel to each other, each of the plurality secondary discharging being arranged to cross the plurality of signal lines, a plurality of first electrostatic discharging units arranged in one-to-one correspondence with the plurality of signal lines, and a primary discharging line connected to the plurality of secondary discharging lines. One end of each first electrostatic discharging unit is connected to its corresponding signal line, and the other end thereof is connected to one of the plurality of secondary discharging lines.

公开(公告)号：US20170287747A1

公开(公告)日：2017-10-05

申请号：US15511432

申请日：2016-02-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaoyong LU ,  Xiaowei XU ,  Yueping ZUO ,  Hongwei TIAN ,  Yu ZHANG ,  Chunping LONG

IPC: H01L21/67 ,  H01L21/66 ,  H01L21/324

CPC classification number: H01L21/67109 ,  H01L21/00 ,  H01L21/324 ,  H01L21/67103 ,  H01L21/67248 ,  H01L21/68742 ,  H01L22/26

Abstract: A substrate heating device and substrate heating method is disclosed. The device comprises: a heating layer for transferring heat; a transfer pipe for transferring a gas to a diffusion layer; the diffusion layer for enabling the gas to be uniformly distributed between a conducting layer and the heating layer; and the conducting layer for conducting the gas in the diffusion layer to below a substrate to be heated. The device can uniformly and fully heat the substrate to be heated, thus enabling the to-be-heated substrate to have a more uniform surface temperature, and achieving a better effect in an etching, deposition and/or sputtering process of the substrate to be heated.

公开(公告)号：US20160254285A1

公开(公告)日：2016-09-01

申请号：US14768009

申请日：2015-01-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping LONG ,  Zuqiang WANG

IPC: H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L27/1244 ,  G02F1/1368 ,  G02F2001/13685 ,  H01L27/1222 ,  H01L27/1274 ,  H01L27/3262 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/78675

Abstract: The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device. The thin film transistor comprises a gate, a source, a drain, a gate insulation layer, an active layer, a passivation layer, a first electrode connection line and a second electrode connection line. The gate, the source and the drain are provided in the same layer and comprise the same material. The gate insulation layer is provided above the gate, the active layer is provided above the gate insulation layer, and a pattern of the gate insulation layer, a pattern of the gate and a pattern of the active layer coincide with each other. The passivation layer covers the source, the drain and the active layer, and the passivation layer has a first via hole corresponding to a position of the source, a second via hole corresponding to a position of the drain, and a third via hole and a fourth via hole corresponding to a position of the active layer provided therein. The first electrode connection line connects the source with the active layer through the first via hole and the third via hole, and the second electrode connection line connects the drain with the active layer through the second via hole and the fourth via hole.

Abstract translation: 本发明提供一种薄膜晶体管及其制造方法，阵列基板及其制造方法以及显示装置。 薄膜晶体管包括栅极，源极，漏极，栅极绝缘层，有源层，钝化层，第一电极连接线和第二电极连接线。 栅极，源极和漏极设置在相同的层中并且包括相同的材料。 栅极绝缘层设置在栅极上方，有源层设置在栅极绝缘层的上方，栅极绝缘层的图案，栅极的图案和有源层的图案彼此重合。 钝化层覆盖源极，漏极和有源层，钝化层具有对应于源极的位置的第一通孔，对应于漏极的位置的第二通孔，以及第三通孔和 第四通孔对应于其中设置的有源层的位置。 第一电极连接线通过第一通孔和第三通孔将源极与有源层连接，第二电极连接线通过第二通孔和第四通孔将漏极与有源层连接。

公开(公告)号：US20160181289A1

公开(公告)日：2016-06-23

申请号：US14646416

申请日：2014-09-23

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping LONG ,  Zheng LIU ,  Zuqiang WANG ,  Jang Soon IM

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/32 ,  H01L29/66

CPC classification number: H01L27/1222 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/1288 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L29/66757 ,  H01L29/78675 ,  H01L2227/323

Abstract: An array substrate and manufacturing method thereof, a display device, a thin film transistor and manufacturing method thereof are provided. The manufacturing method of an array substrate includes forming an active material layer (501), a gate insulating layer (204) and a metal thin film (502) on a base substrate (201), and forming a pattern including an active layer (203) and a pattern including a gate electrode (205), a source electrode (206), a drain electrode (207), a gate line (1063) and a data line (1061) by a first patterning process; forming a passivation layer (301) on the base substrate (201), and forming a source contact hole (302), a drain contact hole (303), and an bridge-structure contact hole (1062a) by a second patterning process; forming a transparent conductive thin film (1401) on the base substrate (201), and removing the transparent conductive thin film (1404) partially, so that a source contact section (401), a drain contact section (402), a pixel electrode (403), and an bridge structure (1062) are formed. With the manufacturing method, the use number of patterning processes is decreased.

Abstract translation: 提供阵列基板及其制造方法，显示装置，薄膜​​晶体管及其制造方法。 阵列基板的制造方法包括在基底基板（201）上形成活性物质层（501），栅极绝缘层（204）和金属薄膜（502），形成包括活性层（203）的图案 ）和通过第一图案化工艺包括栅电极（205），源电极（206），漏电极（207），栅线（1063）和数据线（1061）的图案; 在所述基底基板上形成钝化层，通过第二构图工艺形成源极接触孔，漏极接触孔和桥接结构接触孔; 在所述基底基板上形成透明导电薄膜，将所述透明导电薄膜部分地去除，使得源极接触部分，漏极接触部分，像素电极， （403）和桥结构（1062）。 通过制造方法，图案化处理的使用次数减少。

公开(公告)号：US20140138695A1

公开(公告)日：2014-05-22

申请号：US14081833

申请日：2013-11-15

Applicant: Boe Technology Group Co., Ltd.

Inventor： Xueyan TIAN ,  Chunping LONG

IPC: H01L29/786 ,  H01L21/02

CPC classification number: H01L27/1281 ,  H01L21/02112 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02672 ,  H01L21/02686 ,  H01L27/1262 ,  H01L29/66757 ,  H01L29/78675

Abstract: A method for producing a low temperature polycrystalline silicon thin film, comprising steps of: providing a substrate; forming a thermal conduction and electrical insulation layer, a buffer layer and an amorphous silicon layer on the substrate in this order; and performing a high-temperature treatment and a laser annealing on the amorphous silicon layer to convert the amorphous silicon layer to a polycrystalline silicon thin film, wherein the thermal conduction and electrical insulation layer comprises regular patterns distributed on the substrate.

Abstract translation: 一种生产低温多晶硅薄膜的方法，包括以下步骤：提供基底; 在该基板上依次形成导热和电绝缘层，缓冲层和非晶硅层; 以及对所述非晶硅层进行高温处理和激光退火以将所述非晶硅层转换为多晶硅薄膜，其中所述导热和电绝缘层包括分布在所述基板上的规则图案。

公开(公告)号：US20250113705A1

公开(公告)日：2025-04-03

申请号：US18560169

申请日：2022-11-17

Applicant: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Tong WU ,  Hongli WANG ,  Pan LI ,  Ying HAN ,  Ying CUI ,  Can YUAN ,  Xing ZHANG ,  Ruqin ZHANG ,  Chunping LONG

IPC: H10K59/121 ,  H10K59/122 ,  H10K59/131 ,  H10K59/88

Abstract: Provided are a display substrate and a display device. The display substrate includes a driving transistor and a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, the second electrode plate is arranged in a same layer as the channel of the driving transistor, the second electrode plate is closer to the base substrate than the first electrode plate, an orthographic projection of the second electrode plate on the base substrate overlaps with an orthographic projection of the pixel opening on the base substrate, the display substrate satisfies a following relationship: a value range of (W*L+S2)*M1/M2 is [0.014, 0.133], and a value range of S2/(W*L) is [2.82, 28.85], where W is a width of the channel of the driving transistor, L is a length of the channel of the driving transistor, S2 is a facing area between the second electrode plate and the first electrode plate, M1 is a count of pixel openings in the display substrate, and M2 is an area of the display substrate, thus increasing the facing area between the electrode plates of the storage capacitor, increasing the capacitance, and improving the holding capacity of the capacitor, and being beneficial to increasing the area ratio of the storage capacitor to the pixel opening, increasing the area proportion of the storage capacitor, and improving the display quality.