公开(公告)号：US20170047352A1

公开(公告)日：2017-02-16

申请号：US15340524

申请日：2016-11-01

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.

Inventor： Zuqiang WANG

IPC: H01L27/12

CPC classification number: H01L27/1222 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/26513 ,  H01L21/324 ,  H01L27/127 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675 ,  H01L2029/7863

Abstract: A polysilicon thin film transistor, a manufacturing method thereof, an array substrate involve display technology field, and can repair the boundary defect and the defect state in polysilicon, suppress the hot carrier effect and make the characteristics of TFTs more stable. The polysilicon thin film transistor includes a gate electrode, a source electrode, a drain electrode and an active layer, the active layer comprises at least a channel area, first doped regions, second doped regions and heavily doped regions, and the first doped regions are disposed on two sides of the channel area, the second doped regions are disposed on sides of the first doped regions away from the channel area; the heavily doped regions are disposed on sides of the second doped regions opposed to the first doped regions; and dosage of ions in the heavily doped regions lies between that in the first doped regions and that in the second doped regions.

Abstract translation: 多晶硅薄膜晶体管及其制造方法，阵列基板涉及显示技术领域，可以修复多晶硅中的边界缺陷和缺陷状态，抑制热载流子效应，使TFT的特性更加稳定。 多晶硅薄膜晶体管包括栅电极，源电极，漏电极和有源层，有源层至少包括沟道区，第一掺杂区，第二掺杂区和重掺杂区，第一掺杂区是 设置在通道区域的两侧，第二掺杂区域设置在远离通道区域的第一掺杂区域的侧面上; 重掺杂区域设置在与第一掺杂区域相对的第二掺杂区域的侧面上; 并且重掺杂区域中的离子的剂量位于第一掺杂区域和第二掺杂区域中的离子剂量。

公开(公告)号：US20180145146A1

公开(公告)日：2018-05-24

申请号：US15519948

申请日：2016-01-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang WANG ,  Yuqing YANG

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L29/6675 ,  H01L21/02595 ,  H01L21/02675 ,  H01L27/12 ,  H01L27/1218 ,  H01L27/1274 ,  H01L29/786

Abstract: The present disclosure provides a thin film transistor, a method for manufacturing the same, an array substrate and a display device. The method for manufacturing a thin film transistor includes providing a substrate, forming a gate electrode, a gate insulating layer, an amorphous silicon material active layer and a cap layer on the substrate successively, wherein The cap layer is provided with a pattern on a side of the cap layer away from the amorphous silicon material active layer, and the pattern is composed of at least one groove along a length direction of the active layer and at least one groove along a width direction of the active layer, subjecting the amorphous silicon material active layer to laser annealing treatment to transform the amorphous silicon material active layer into a low temperature polycrystalline silicon material active layer, and removing the cap layer.

公开(公告)号：US20190288014A1

公开(公告)日：2019-09-19

申请号：US16078319

申请日：2018-01-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang WANG

IPC: H01L27/12

Abstract: A display panel includes: a base substrate; a peripheral circuit located on the base substrate, the peripheral circuit including a first circuit, a second circuit and a third circuit, and the first circuit, the second circuit and the third circuit respectively including a first electrode pattern, a second electrode pattern and a third electrode pattern; and a protection structure, located in at least one circuit of the first circuit, the second circuit and the third circuit and configured for preventing an electrode pattern from being disconnected.

公开(公告)号：US20160254287A1

公开(公告)日：2016-09-01

申请号：US14769180

申请日：2014-12-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zuqiang WANG ,  Chien Hung LIU

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/124 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  H01L29/06 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/786

Abstract: A thin-film transistor (TFT), a manufacturing method thereof, display substrate and a display device are disclosed. The TFT includes: an active layer, gate insulating layer, gate electrode, an interlayer dielectric layer, source electrode and a drain electrode disposed on a base substrate in sequence. The source electrode and drain electrode are respectively connected with the active layer via a through hole exposing the active layer; the gate insulating layer at least includes a silicon oxide layer and a silicon nitride layer in a two-layer structure; the interlayer dielectric layer at least includes silicon oxide layers and silicon nitride layers in a four-layer structure; the silicon oxide layers and silicon nitride layers of the gate insulating layer and the interlayer dielectric layer are alternately arranged; and the dimension of one side of the through hole away from the base substrate is greater than that of one side close to the base substrate.

Abstract translation: 公开了薄膜晶体管（TFT），其制造方法，显示基板和显示装置。 TFT包括：有源层，栅极绝缘层，栅极电极，层间电介质层，源电极和设置在基底基板上的漏电极。 源电极和漏极分别通过暴露有源层的通孔与有源层连接; 栅极绝缘层至少包括二层结构的氧化硅层和氮化硅层; 层间绝缘层至少包括四层结构的氧化硅层和氮化硅层; 栅极绝缘层和层间电介质层的氧化硅层和氮化硅层交替排列; 并且通孔的远离基底的一侧的尺寸大于靠近基底的一侧的尺寸。

公开(公告)号：US20150340389A1

公开(公告)日：2015-11-26

申请号：US14402532

申请日：2013-12-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng LIU ,  Jangsoon IM ,  Zuqiang WANG

IPC: H01L27/12

CPC classification number: H01L27/1274 ,  H01L27/1255 ,  H01L27/1262

Abstract: The present invention provides a method for manufacturing an array substrate, an array substrate, and a display device. The method for manufacturing an array substrate, including a step of forming a thin film transistor and a storage capacitor on a substrate, the thin film transistor including a gate, a source, and a drain, and the storage capacitor including a first pole plate and a second pole plate, wherein, arranging the source, the drain, and the first pole plate in a single layer through implanting dopant ions into an amorphous silicon layer formed on the substrate by one ion-implantation process, and through crystallizing an amorphous silicon material forming the amorphous silicon layer and activating the dopant ions by a laser irradiation process. Accordingly, process steps are simplified and a process cost is reduced greatly, and the performances of the array substrate and the display device are increased.

Abstract translation: 本发明提供一种阵列基板，阵列基板和显示装置的制造方法。 制造阵列基板的方法，包括在基板上形成薄膜晶体管和存储电容的步骤，所述薄膜晶体管包括栅极，源极和漏极，所述存储电容器包括第一极板和 第二极板，其中，通过一个离子注入工艺将源极，漏极和第一极板设置在单层中，通过将掺杂剂离子注入到形成在衬底上的非晶硅层中，并且通过使非晶硅材料结晶 形成非晶硅层并通过激光照射工艺激活掺杂剂离子。 因此，简化了处理步骤，并且大大降低了处理成本，并且增加了阵列基板和显示装置的性能。

公开(公告)号：US20170168330A1

公开(公告)日：2017-06-15

申请号：US15322549

申请日：2016-04-15

Applicant: Boe Technology Group Co., Ltd.

Inventor： Zuqiang WANG ,  Guang LI ,  Liang SUN ,  Xiaoyong LU

IPC: G02F1/13 ,  G02F1/1362 ,  G02F1/1333 ,  G02F1/1368 ,  H01L27/32 ,  G01R31/28

CPC classification number: G02F1/1309 ,  G01R31/2825 ,  G02F1/133345 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136254 ,  G02F2001/136295 ,  G09G3/006 ,  G09G3/3208 ,  G09G2300/0417 ,  H01L21/77 ,  H01L22/34 ,  H01L27/3262 ,  H01L2227/323

Abstract: A display panel comprises a display area and a peripheral area around the display area. The peripheral area comprises: an electroluminescent layer test region, a TFT test region and a plurality of lead-out lines. The electroluminescent layer test region comprises a plurality of thin film transistors having electroluminescent layers, a first test line connecting sources of the plurality of thin film transistors having electroluminescent layers, and a switch lead and a second test line connecting gates of the plurality of thin film transistors having electroluminescent layers. The TFT test region comprises a plurality of thin film transistors. Each of the plurality of lead-out lines is used for connecting a source-drain metal layer of one thin film transistor in the electroluminescent layer test region and a source-drain metal layer of one thin film transistor in the TFT test region.

公开(公告)号：US20160254285A1

公开(公告)日：2016-09-01

申请号：US14768009

申请日：2015-01-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping LONG ,  Zuqiang WANG

IPC: H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L27/1244 ,  G02F1/1368 ,  G02F2001/13685 ,  H01L27/1222 ,  H01L27/1274 ,  H01L27/3262 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/78675

Abstract: The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device. The thin film transistor comprises a gate, a source, a drain, a gate insulation layer, an active layer, a passivation layer, a first electrode connection line and a second electrode connection line. The gate, the source and the drain are provided in the same layer and comprise the same material. The gate insulation layer is provided above the gate, the active layer is provided above the gate insulation layer, and a pattern of the gate insulation layer, a pattern of the gate and a pattern of the active layer coincide with each other. The passivation layer covers the source, the drain and the active layer, and the passivation layer has a first via hole corresponding to a position of the source, a second via hole corresponding to a position of the drain, and a third via hole and a fourth via hole corresponding to a position of the active layer provided therein. The first electrode connection line connects the source with the active layer through the first via hole and the third via hole, and the second electrode connection line connects the drain with the active layer through the second via hole and the fourth via hole.

Abstract translation: 本发明提供一种薄膜晶体管及其制造方法，阵列基板及其制造方法以及显示装置。 薄膜晶体管包括栅极，源极，漏极，栅极绝缘层，有源层，钝化层，第一电极连接线和第二电极连接线。 栅极，源极和漏极设置在相同的层中并且包括相同的材料。 栅极绝缘层设置在栅极上方，有源层设置在栅极绝缘层的上方，栅极绝缘层的图案，栅极的图案和有源层的图案彼此重合。 钝化层覆盖源极，漏极和有源层，钝化层具有对应于源极的位置的第一通孔，对应于漏极的位置的第二通孔，以及第三通孔和 第四通孔对应于其中设置的有源层的位置。 第一电极连接线通过第一通孔和第三通孔将源极与有源层连接，第二电极连接线通过第二通孔和第四通孔将漏极与有源层连接。

公开(公告)号：US20160181289A1

公开(公告)日：2016-06-23

申请号：US14646416

申请日：2014-09-23

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping LONG ,  Zheng LIU ,  Zuqiang WANG ,  Jang Soon IM

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/32 ,  H01L29/66

CPC classification number: H01L27/1222 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/1288 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L29/66757 ,  H01L29/78675 ,  H01L2227/323

Abstract: An array substrate and manufacturing method thereof, a display device, a thin film transistor and manufacturing method thereof are provided. The manufacturing method of an array substrate includes forming an active material layer (501), a gate insulating layer (204) and a metal thin film (502) on a base substrate (201), and forming a pattern including an active layer (203) and a pattern including a gate electrode (205), a source electrode (206), a drain electrode (207), a gate line (1063) and a data line (1061) by a first patterning process; forming a passivation layer (301) on the base substrate (201), and forming a source contact hole (302), a drain contact hole (303), and an bridge-structure contact hole (1062a) by a second patterning process; forming a transparent conductive thin film (1401) on the base substrate (201), and removing the transparent conductive thin film (1404) partially, so that a source contact section (401), a drain contact section (402), a pixel electrode (403), and an bridge structure (1062) are formed. With the manufacturing method, the use number of patterning processes is decreased.

Abstract translation: 提供阵列基板及其制造方法，显示装置，薄膜​​晶体管及其制造方法。 阵列基板的制造方法包括在基底基板（201）上形成活性物质层（501），栅极绝缘层（204）和金属薄膜（502），形成包括活性层（203）的图案 ）和通过第一图案化工艺包括栅电极（205），源电极（206），漏电极（207），栅线（1063）和数据线（1061）的图案; 在所述基底基板上形成钝化层，通过第二构图工艺形成源极接触孔，漏极接触孔和桥接结构接触孔; 在所述基底基板上形成透明导电薄膜，将所述透明导电薄膜部分地去除，使得源极接触部分，漏极接触部分，像素电极， （403）和桥结构（1062）。 通过制造方法，图案化处理的使用次数减少。