公开(公告)号：US20120256260A1

公开(公告)日：2012-10-11

申请号：US13082491

申请日：2011-04-08

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66742 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78648

摘要： Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks.

摘要翻译： 通过首先构图顶部半导体层和掩埋绝缘体层来形成与有源区域自对准的掺杂半导体背栅极区域，以形成埋入绝缘体部分和半导体部分的堆叠。 将氧气以一定角度注入到下面的半导体层中，使得注氧区域形成在不被叠层或掩模结构遮蔽的区域中。 氧注入部分被转换成深沟槽隔离结构，其与作为堆叠中的半导体部分的有源区的侧壁自对准。 将掺杂离子注入深沟槽隔离结构之间的底层半导体层的部分，以形成掺杂半导体背栅区。 在深沟槽隔离结构和堆叠之间形成浅沟槽隔离结构。

公开(公告)号：US20100203717A1

公开(公告)日：2010-08-12

申请号：US12698448

申请日：2010-02-02

申请人： Sivananda K. Kanakasabapathy ,  Veeraraghavan S. Basker ,  Balasubramanian S. Haran

发明人： Sivananda K. Kanakasabapathy ,  Veeraraghavan S. Basker ,  Balasubramanian S. Haran

IPC分类号： H01L21/28

CPC分类号： H01L29/4238 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/32139

摘要： A multiple etch process for forming a gate in a semiconductor structure in which a cut area is first formed followed by the forming of the gate conductor lines.

摘要翻译： 在半导体结构中形成栅极的多次蚀刻工艺，其中首先形成切割区域，之后形成栅极导体线。

公开(公告)号：US08673738B2

公开(公告)日：2014-03-18

申请号：US13531780

申请日：2012-06-25

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC分类号： H01L21/76

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

摘要翻译： 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

公开(公告)号：US08673708B2

公开(公告)日：2014-03-18

申请号：US13611044

申请日：2012-09-12

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

摘要： A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing a layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening.

摘要翻译： 一种方法包括提供绝缘体上硅晶片（例如，ETSOI晶片）; 形成覆盖牺牲绝缘体层的牺牲栅极结构; 形成与牺牲栅极结构相邻的凸起的源极/漏极; 沉积覆盖升高的源极/漏极并围绕牺牲栅极结构的层; 以及去除牺牲栅极结构，留下延伸到牺牲绝缘体层的开口。 该方法还包括加宽开口以暴露一些升高的源极/漏极，去除牺牲绝缘体层并在开口的侧壁上形成间隔层，间隔层仅覆盖暴露的升高的源极/漏极的上部 ，并且在开口内沉积一层栅介质材料。 栅极导体沉积在开口内。

公开(公告)号：US20140061582A1

公开(公告)日：2014-03-06

申请号：US13600324

申请日：2012-08-31

申请人： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

发明人： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

IPC分类号： H01L29/06 ,  H01L21/20 ,  B82Y40/00

CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3086 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/78696 ,  Y10S977/938

摘要： A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.

摘要翻译： 具有垂直平面的心轴形成在单晶半导体层上。 通过选择性外延在单晶半导体层上形成外延半导体层。 围绕心轴的上部形成第一间隔件。 使用第一间隔物作为蚀刻掩模，外延半导体层垂直凹入。 在第一间隔物的侧壁和外延半导体层的垂直部分上形成第二间隔物。 从外延半导体层的垂直部分的下方蚀刻外延半导体层的水平底部部分，以形成附接到心轴的悬挂的环形半导体鳍片。 使用覆盖心轴的两个端部的图案化掩模层来蚀刻心轴的中心部分。 提供悬挂的半导体鳍片，其由一对支撑结构悬挂。

公开(公告)号：US08629008B2

公开(公告)日：2014-01-14

申请号：US13348018

申请日：2012-01-11

申请人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L21/02

CPC分类号： H01L29/0653 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654

摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.

摘要翻译： 在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。 随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。 平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。 通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。 沉积至少一个接触电介质层。 可以在接触通孔内形成与手柄基板电隔离的结构的接触。

公开(公告)号：US20130292766A1

公开(公告)日：2013-11-07

申请号：US13463402

申请日：2012-05-03

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor integrated circuit is provided and includes a first field effect transistor (FET) device and a second FET device formed on a semiconductor substrate. The first FET device has raised source/drain (RSD) structures grown at a first height. The second FET device has RSD structures grown at a second height greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.

摘要翻译： 提供了半导体集成电路，并且包括形成在半导体衬底上的第一场效应晶体管（FET）器件和第二FET器件。 第一FET器件提高了在第一高度生长的源极/漏极（RSD）结构。 第二FET器件具有在大于第一高度的第二高度处生长的RSD结构，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

公开(公告)号：US20130249002A1

公开(公告)日：2013-09-26

申请号：US13424447

申请日：2012-03-20

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0653 ,  H01L21/76224 ,  H01L21/84 ,  H01L29/66545

摘要： A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in said hole.

摘要翻译： 改进ETSOI MOSFET器件的结构和方法。 提供晶片，其包括具有覆盖在第二半导体层上的氧化物层的至少第一半导体层的区域。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 栅极结构形成在第一半导体层之上，并且在涉及的湿清洗期间，STI纹理腐蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔不完全落地，至少部分地延伸到STI中，并且绝缘材料沉积在所述孔中。

公开(公告)号：US20130175622A1

公开(公告)日：2013-07-11

申请号：US13348018

申请日：2012-01-11

申请人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0653 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654

摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.

摘要翻译： 在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。 随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。 平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。 通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。 沉积至少一个接触电介质层。 可以在接触通孔内形成与手柄基板电隔离的结构的接触。

公开(公告)号：US20130175579A1

公开(公告)日：2013-07-11

申请号：US13347161

申请日：2012-01-10

申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Sivananda Kanakasabapathy ,  Pranita Kulkarni ,  Balasubramanian S. Haran

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Sivananda Kanakasabapathy ,  Pranita Kulkarni ,  Balasubramanian S. Haran

IPC分类号： H01L29/78 ,  H01L21/335

CPC分类号： H01L29/66795 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

摘要： A transistor includes a first semiconductor layer. A second semiconductor layer is located on the first semiconductor layer. A portion of the second semiconductor layer is removed to expose a first portion of the first semiconductor layer and to provide vertical sidewalls of the second semiconductor layer. A gate spacer is located on the second semiconductor layer. A gate dielectric includes a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer. A gate conductor is located on the first portion of the gate dielectric and abuts the gate dielectric second portion. A channel region is located in at least part of the first portion of the first semiconductor layer. Raised source/drain regions are located in the second semiconductor layer. At least part of the raised source/drain regions is located below the gate spacer.

摘要翻译： 晶体管包括第一半导体层。 第二半导体层位于第一半导体层上。 去除第二半导体层的一部分以暴露第一半导体层的第一部分并提供第二半导体层的垂直侧壁。 栅极间隔物位于第二半导体层上。 栅极电介质包括位于第一半导体层的第一部分上的第一部分和与第二半导体层的垂直侧壁相邻的第二部分。 栅极导体位于栅极电介质的第一部分上并邻接栅极电介质第二部分。 沟道区位于第一半导体层的第一部分的至少一部分中。 上升的源极/漏极区域位于第二半导体层中。 凸起的源极/漏极区域的至少一部分位于栅极间隔物的下方。