公开(公告)号：US20090168498A1

公开(公告)日：2009-07-02

申请号：US12006063

申请日：2007-12-28

申请人： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

发明人： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

IPC分类号： G11C11/40 ,  H01L21/283

CPC分类号： H01L27/1104 ,  H01L27/0207

摘要： In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.

摘要翻译： 通常，一方面，一种方法包括形成具有N-扩散和P-扩散区域的半导体衬底。 在半导体衬底上形成栅叠层。 栅电极硬掩模形成在栅叠层上。 栅极电极硬掩模用隔离材料增加在通过栅极晶体管周围。 使用增强的栅极电极硬掩模蚀刻栅极堆叠以形成栅电极。 通过栅极周围的栅电极具有比其它栅电极更大的长度。

公开(公告)号：US20090166742A1

公开(公告)日：2009-07-02

申请号：US11964623

申请日：2007-12-26

申请人： Ravi Pillarisetty ,  Uday Shah ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

发明人： Ravi Pillarisetty ,  Uday Shah ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

IPC分类号： H01L29/94 ,  H01L21/8234

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.

摘要翻译： 通常描述通过结合部分金属翅片来降低多栅极器件的外部电阻。 在一个示例中，设备包括半导体衬底和与半导体衬底耦合的多栅极晶体管器件的一个或多个鳍片，该一个或多个鳍片具有栅极区域，源极区域和漏极区域，栅极区域 设置在源极和漏极区域之间，其中一个或多个鳍片的栅极区域包括半导体材料，并且其中一个或多个鳍片的源极和漏极区域包括金属部分和半导体部分，金属部分和半导体 部分联接在一起。

公开(公告)号：US20090166741A1

公开(公告)日：2009-07-02

申请号：US11964593

申请日：2007-12-26

申请人： Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

发明人： Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/66545 ,  H01L29/785

摘要： Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.

摘要翻译： 通常描述使用间隔物处理技术降低多栅极器件的外部电阻。 在一个示例中，一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上，一个或多个多栅极鳍片包括栅极区域，源极区域和漏极区域，栅极区域设置在 源极和漏极区域，图案化牺牲栅极电极，使得牺牲栅电极材料耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到一个或多个多栅极鳍片的源极和漏极区域，形成电介质 薄膜耦合到一个或多个多栅极鳍片的源极和漏极区域，从一个或多个多栅极鳍片的栅极区域去除牺牲栅电极，将间隔栅极电介质沉积到该一个或多个多栅极散热片的栅极区域 多栅极翅片，其中基本上没有间隔栅极电介质沉积到一个或多个多栅极鳍片的源极和漏极区域，源极和漏极区域被电介质fi 并且蚀刻间隔栅极电介质，以将栅极区域的栅极区域完全去除以与最终栅电极耦合的间隔栅极电介质，除了要与保持耦合的最终栅电极耦合的间隔栅极电介质的剩余预定厚度 与电介质膜。

公开(公告)号：US20150091067A1

公开(公告)日：2015-04-02

申请号：US14040574

申请日：2013-09-27

申请人： Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  David L. Kencke ,  Uday Shah ,  Charles C. Kuo ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  David L. Kencke ,  Uday Shah ,  Charles C. Kuo ,  Robert S. Chau

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L27/2436 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L2029/7858

摘要： An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

摘要翻译： 在晶体管结构上沉积绝缘层。 晶体管结构包括位于衬底上的器件层上的栅电极。 晶体管结构包括在栅电极的相对侧的器件层上的第一接触区域和第二接触区域。 在第一接触区域上的第一绝缘层中形成沟槽。 具有S形IV特性的金属 - 绝缘体相变材料层沉积在源极侧上方的金属化层的沟槽或通路中。

公开(公告)号：US20110284965A1

公开(公告)日：2011-11-24

申请号：US13204987

申请日：2011-08-08

申请人： Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

发明人： Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

IPC分类号： H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/66545 ,  H01L29/785

摘要： Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more to multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.

摘要翻译： 通常描述使用间隔物处理技术降低多栅极器件的外部电阻。 在一个示例中，一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上，一个或多个多栅极鳍片包括栅极区域，源极区域和漏极区域，栅极区域设置在 源极和漏极区域，图案化牺牲栅极电极，使得牺牲栅电极材料耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到一个或多个多栅极鳍片的源极和漏极区域，形成电介质 将一个或多个多栅极翅片的源极和漏极区域耦合到所述一个或多个多栅极散热片的栅极区域;将所述牺牲栅极电极从所述一个或多个至多个栅极鳍片的栅极区域移除;将间隔栅极电介质沉积到所述一个或多个栅极栅极栅极区域; 更多的多栅极鳍片，其中基本上没有间隔栅极电介质沉积到一个或多个多栅极鳍片的源极和漏极区域，源极和漏极区域被电介质保护 膜和蚀刻间隔栅极电介质以从栅极区域区域完全去除间隔栅极电介质，以与最终栅极电极耦合，除了与保持耦合的最终栅电极耦合的间隔栅极电介质的剩余预定厚度之外 与电介质膜。

公开(公告)号：US20110260244A1

公开(公告)日：2011-10-27

申请号：US13178974

申请日：2011-07-08

申请人： Brian S. Doyle ,  Gilbert Dewey ,  Ravi Pillarisetty ,  Nick Lindert ,  Uday Shah ,  Dinesh Somasekhar

发明人： Brian S. Doyle ,  Gilbert Dewey ,  Ravi Pillarisetty ,  Nick Lindert ,  Uday Shah ,  Dinesh Somasekhar

IPC分类号： H01L27/092

CPC分类号： H01L21/823456 ,  H01L21/82345 ,  H01L21/823462 ,  H01L29/4236 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： Embodiments of the invention relate to a method of fabricating logic transistors using replacement metal gate (RMG) logic flow with modified process to form recessed channel array transistors (RCAT) on a common semiconductor substrate. An embodiment comprises forming an interlayer dielectric (ILD) layer on a semiconductor substrate, forming a first recess in the ILD layer of a first substrate region, forming a recessed channel in the ILD layer and in the substrate of a second substrate region, depositing a first conformal high-k dielectric layer in the first recess and a second conformal high-k dielectric layer in the recessed channel, and filling the first recess with a first gate metal and the recessed channel with a second gate metal.

摘要翻译： 本发明的实施例涉及使用具有修改过程的替代金属栅（RMG）逻辑流来制造逻辑晶体管的方法，以在公共半导体衬底上形成凹陷沟道阵列晶体管（RCAT）。 一个实施例包括在半导体衬底上形成层间绝缘层（ILD）层，在第一衬底区域的ILD层中形成第一凹槽，在第一衬底区域的ILD层和衬底中形成凹陷沟道， 第一凹部中的第一共形高k电介质层和凹陷沟道中的第二共形高k电介质层，并且用第一栅极金属填充第一凹槽，并且利用第二栅极金属填充凹陷沟道。

公开(公告)号：US07825437B2

公开(公告)日：2010-11-02

申请号：US12006082

申请日：2007-12-28

申请人： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

发明人： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

IPC分类号： H01L27/118

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate.

摘要翻译： 通常，在一个方面，一种方法包括在半导体衬底中形成N-扩散和P-扩散翅片。 在半导体衬底上形成P扩散栅极层，并从N扩散鳍片上去除。 在半导体衬底上形成通过栅极的N扩散栅极层，并从P扩散鳍片和下拉的N扩散鳍片中去除。 在半导体衬底上形成下拉式N扩散层。

公开(公告)号：US07820512B2

公开(公告)日：2010-10-26

申请号：US12006063

申请日：2007-12-28

申请人： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

发明人： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/311

CPC分类号： H01L27/1104 ,  H01L27/0207

摘要： In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.

摘要翻译： 通常，一方面，一种方法包括形成具有N-扩散和P-扩散区域的半导体衬底。 在半导体衬底上形成栅叠层。 栅电极硬掩模形成在栅叠层上。 栅极电极硬掩模用隔离材料增加在通过栅极晶体管周围。 使用增强的栅极电极硬掩模蚀刻栅极堆叠以形成栅电极。 通过栅极周围的栅电极具有比其它栅电极更大的长度。

公开(公告)号：US20090166680A1

公开(公告)日：2009-07-02

申请号：US12006082

申请日：2007-12-28

申请人： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

发明人： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate.

摘要翻译： 通常，在一个方面，一种方法包括在半导体衬底中形成N-扩散和P-扩散翅片。 在半导体衬底上形成P扩散栅极层，并从N扩散鳍片上去除。 在半导体衬底上形成通过栅极的N扩散栅极层，并从P扩散鳍片和下拉的N扩散鳍片中去除。 在半导体衬底上形成下拉式N扩散层。

公开(公告)号：US20180350418A1

公开(公告)日：2018-12-06

申请号：US15779029

申请日：2015-12-24

申请人： Brian S. Doyle ,  Elijah V. Karpov ,  Kaan Oguz ,  Kevin P. O'Brien ,  Charles C. Kuo ,  Mark L. Doczy ,  Uday Shah ,  Yih Wang

发明人： Brian S. Doyle ,  Elijah V. Karpov ,  Kaan Oguz ,  Kevin P. O'Brien ,  Charles C. Kuo ,  Mark L. Doczy ,  Uday Shah ,  Yih Wang

IPC分类号： G11C11/16 ,  G11C11/56 ,  H01L43/08 ,  H01L27/22

CPC分类号： G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C2211/5615 ,  H01L27/228 ,  H01L43/08

摘要： Memory cells with improved tunneling magnetoresistance ratio (TMR) are disclosed. In some embodiments such devices may include a magnetoresistive tunnel junction (MTJ) element coupled in series with a tunneling magnetoresistance enhancement element (TMRE). The MTJ element and TMRE may each be configured to transition between high and low resistance states, e.g., in response to a voltage. In some embodiments, the MTJ and TMRE are configure such that when a read voltage is applied to the cell while the MTJ is in its low resistance state the TMRE is driven to is low resistance state, and when such voltage is applied while the MTJ is in its high resistance state, the TMRE remains in its high resistance state. Devices and systems including such memory cells are also disclosed.