公开(公告)号：US11163929B1

公开(公告)日：2021-11-02

申请号：US16735672

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： William Robert Reece ,  Thomas Andrew Newton ,  Ruth Patricia Jackson ,  Zhuo Li

IPC: G06F30/337 ,  G06F117/04 ,  G06F30/398 ,  G06F119/12

Abstract: Various embodiments provide for clock network generation for a circuit design using an inverting integrated clock gate (ICG). According to some embodiments, a clock network with one or more inverting ICGs is generated, after a topology of the clock network is defined, by applying a non-inverting ICG-to-inverting ICG transform to one or more nodes of the clock network that comprise a non-inverting ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more inverting ICGs.

公开(公告)号：US11132490B1

公开(公告)日：2021-09-28

申请号：US16735674

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Ruth Patricia Jackson ,  William Robert Reece ,  Thomas Andrew Newton ,  Zhuo Li

IPC: G06F30/396 ,  G06F30/398 ,  G06F119/12 ,  G06F117/04

Abstract: Various embodiments provide for clock network generation for a circuit design using a negative-edge integrated clock gate (ICG). According to some embodiments, a clock network with one or more negative-edge ICGs is generated, after a topology of the clock network is defined, by applying a positive-edge ICG-to-negative-edge ICG transform to one or more nodes of the clock network that comprise a positive-edge ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more negative-edge ICGs.

公开(公告)号：US11132489B1

公开(公告)日：2021-09-28

申请号：US16805155

申请日：2020-02-28

Applicant: Cadence Design Systems, Inc.

Inventor： Derong Liu ,  Yi-Xiao Ding ,  Zhuo Li ,  Mehmet Can Yildiz

IPC: G06F30/3947 ,  G06F30/398 ,  G06F30/392

Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of the net based on the wirelength threshold.

公开(公告)号：US10936783B1

公开(公告)日：2021-03-02

申请号：US16735669

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Andrew Mark Chapman ,  Zhuo Li

IPC: G06F30/00 ,  G06F30/394 ,  G06F30/392 ,  G06K9/62 ,  G06F30/31

Abstract: Aspects of the present disclosure address improved systems and methods for runtime efficient circuit placement location selection as described herein. An example embodiment includes identifying, for each route of the one or more routes that interconnect the terminals of a circuit design with the one or more pins of a first circuit element, a corresponding set of movement positions along said each route to generate a set of movement configurations for the first circuit element. The set of movement configurations is analyzed to generate a plurality of location clusters from the set of movement configurations, and for each location cluster of the plurality of location clusters, identifying one or more selected movement configurations within said each cluster. The one or more selected movement configurations for said each cluster to select an updated movement configuration.

公开(公告)号：US10929589B1

公开(公告)日：2021-02-23

申请号：US16823998

申请日：2020-03-19

Applicant: Cadence Design Systems, Inc.

Inventor： Dirk Meyer ,  Zhuo Li

IPC: G06F30/00 ,  G06F30/396 ,  G06F30/394 ,  G06F30/31

Abstract: Various embodiments provide for generating a routing structure for a clock network based on edge interaction detection, which can facilitate detection/consideration of overuse of routing resources to a balanced routing structure and which may be part of electronic design automation (EDA) of a circuit design. For example, some embodiments use an edge intersection check to detect overuse of routing resources within the routing structure for a clock network.

公开(公告)号：US10860764B1

公开(公告)日：2020-12-08

申请号：US16731912

申请日：2019-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Jhih-Rong Gao ,  Zhuo Li

IPC: G06F30/3312 ,  G06F30/337 ,  G06F30/392 ,  G06F30/3947 ,  G06F30/398 ,  G06F119/12 ,  G06F111/04 ,  G06F117/10

Abstract: Aspects of the present disclosure address improved systems and methods for layer assignment to improve timing in integrated circuit (IC) designs. An initial placement layout of a net of an IC design is accessed. A plurality of buffer insertion candidates is generated using multiple candidate buffer insertion points and multiple layer assignments from among multiple layers of the IC design. Timing characteristics of each buffer insertion candidate are determined, and timing improvements provided by each buffer insertion candidate are determined based on respective timing characteristics. A buffer insertion candidate is selected from the plurality of buffer insertion candidates based on the timing improvement provided by the buffer insertion candidate. A layout instance for the IC is generated based in part on the selected buffer insertion candidate.

公开(公告)号：US10769345B1

公开(公告)日：2020-09-08

申请号：US16228451

申请日：2018-12-20

Applicant: Cadence Design Systems, Inc.

Inventor： Andrew Mark Chapman ,  Zhuo Li

IPC: G06F17/50 ,  G06F30/396 ,  G06F30/392 ,  G06F30/398 ,  G06F30/3312 ,  G06F30/3953 ,  G06F30/394 ,  G06F111/04 ,  G06F119/12 ,  G06F30/337 ,  G06F30/3947 ,  G06F30/30 ,  G06F30/39

Abstract: Aspects of the present disclosure address improved systems and methods for core-route-based clock tree wirelength reduction. A method may include accessing an integrated circuit design comprising a clock tree comprising routes that interconnect terminals of a plurality of clock tree instances. The method further includes identifying a core route in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and the core route and determining a second offset based on a distance from the second terminal to the core route. The method further includes determining a target offset based on a combination of the first and second offsets and moving the clock tree instance toward the core route by the target offset.

公开(公告)号：US10740532B1

公开(公告)日：2020-08-11

申请号：US16228432

申请日：2018-12-20

Applicant: Cadence Design Systems, Inc.

Inventor： William Robert Reece ,  Thomas Andrew Newton ,  Zhuo Li

IPC: G06F17/50 ,  G06F30/396 ,  G06F30/392 ,  G06F30/327 ,  G06F30/394 ,  G06F117/10 ,  G06F30/30 ,  G06F30/39

Abstract: Aspects of the present disclosure address improved systems and methods for generating a clock tree based on route-driven placement of fan-out clock drivers. Consistent with some embodiments, a method may include constructing a spanning tree comprising one or more paths that interconnect a set of clock sinks of a clock net of an integrated circuit device design. The method further includes calculating a center of the set of the clock sinks based on clock sink locations in the integrated circuit device design and identifying a point on the spanning tree nearest to the center of the set of clock sinks. The method further includes generating a clock tree by placing a clock driver at the point on the spanning tree that is nearest to the center of the set of clock sinks.

公开(公告)号：US10579767B1

公开(公告)日：2020-03-03

申请号：US15640999

申请日：2017-07-03

Applicant: Cadence Design Systems, Inc.

Inventor： Zhuo Li ,  Wen-Hao Liu ,  Gracieli Posser ,  Charles Jay Alpert ,  Ruth Patricia Jackson

IPC: G06F17/50

Abstract: Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.

公开(公告)号：US10460065B1

公开(公告)日：2019-10-29

申请号：US15649426

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Wen-Hao Liu ,  Wing-Kai Chow ,  Gracieli Posser ,  Mehmet Can Yildiz ,  Zhuo Li ,  Charles Jay Alpert

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.