公开(公告)号：US07705340B2

公开(公告)日：2010-04-27

申请号：US11163118

申请日：2005-10-05

申请人： Chun-Chieh Lin

发明人： Chun-Chieh Lin

IPC分类号： H01L47/00

CPC分类号： H01L27/228 ,  H01L43/08

摘要： Disclosed herein is a magnetoresistive structure having a non-planar form. Embodiments of the present MR structure includes those having at least one inflection between a first portion of the MR structure that is somewhat vertical relative to a substrate and a second portion of the MR structure that is somewhat horizontal relative to the substrate. Such a structure can be used for memory device, for example an MRAM memory device, wherein the memory density is increased compared to devices having prior planar MR structures without reducing the surface area of the MR structures.

摘要翻译： 本文公开了具有非平面形式的磁阻结构。 本发明的MR结构的实施例包括那些在MR结构的第一部分之间相对于衬底稍微垂直的第一部分和MR结构相对于衬底稍微水平的第二部分的至少一个拐点。 这种结构可以用于存储器件，例如MRAM存储器件，其中与具有先前的平面MR结构的器件相比，存储器密度增加而不减小MR结构的表面积。

公开(公告)号：US07656433B2

公开(公告)日：2010-02-02

申请号：US11707967

申请日：2007-02-20

申请人： Chi-Hsien Wang ,  Wen-Ming Huang ,  Wei-Song Yeh ,  Chun-Chieh Lin ,  Kuan-Chou Chen

发明人： Chi-Hsien Wang ,  Wen-Ming Huang ,  Wei-Song Yeh ,  Chun-Chieh Lin ,  Kuan-Chou Chen

IPC分类号： H04N5/228 ,  H04N5/225 ,  H04N7/26

CPC分类号： H04N19/184 ,  H04N19/91

摘要： A web camera includes an image sensor, which takes an external image; a sensor interface, which is connected to the mage sensor to receive and convert the image taken by the image sensor into digital image data; at least one compression module, which is connected to the sensor interface to receive and compress the digital image data into compressed image data; and a USB interface, which is connected to the compression module to output the compressed image data to a host device having a USB interface port, such as a computer and a USB OTG device, for storage, playing back and other applications.

摘要翻译： 网络摄像机包括拍摄外部图像的图像传感器; 传感器接口，其连接到法师传感器，以将图像传感器拍摄的图像接收并转换为数字图像数据; 至少一个压缩模块，其连接到传感器接口以将数字图像数据接收并压缩成压缩图像数据; 以及USB接口，其连接到压缩模块以将压缩的图像数据输出到具有诸如计算机和USB OTG设备的USB接口端口的主机设备，用于存储，回放和其他应用。

公开(公告)号：US07592619B2

公开(公告)日：2009-09-22

申请号：US11622490

申请日：2007-01-12

申请人： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

发明人： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC分类号： H01L29/15

CPC分类号： C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

摘要： A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

摘要翻译： 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US20090000908A1

公开(公告)日：2009-01-01

申请号：US12218625

申请日：2008-07-15

申请人： Michael D. Brain ,  Chun-Chieh Lin

发明人： Michael D. Brain ,  Chun-Chieh Lin

IPC分类号： B65G49/07 ,  G06F7/00

CPC分类号： B65G37/005 ,  B65G37/02 ,  B65G2201/0297 ,  H01L21/67276 ,  H01L21/67715 ,  H01L21/67769

摘要： A system for buffering articles in transport is provided. The system comprises a buffer module configured to buffer articles and a computing system. The buffer module includes a first conveyor configured to transport the articles and a transference node configured to transfer the articles between the first conveyor and an external location. The computing system is configured to maintain an inventory list including a present location of each of the articles buffered by the buffer module. The computing system is further configured to control operation of the buffer module to transfer a selected article among the buffered articles to the external location.

摘要翻译： 提供了一种用于在运输中缓冲物品的系统。 该系统包括被配置为缓冲物品和计算系统的缓冲模块。 缓冲器模块包括构造成输送物品的第一传送器和被配置成在第一传送器和外部位置之间传送物品的传送节点。 计算系统被配置为维护包括由缓冲器模块缓冲的每个文章的当前位置的清单列表。 计算系统还被配置为控制缓冲器模块的操作以将缓冲的物品中的所选物品传送到外部位置。

公开(公告)号：US20080265256A1

公开(公告)日：2008-10-30

申请号：US11796369

申请日：2007-04-27

申请人： Chun-Chieh Lin ,  Wei-Hua Hsu ,  Yu-En Percy Chang ,  Chung Li Chang ,  Chi-Feng Cheng ,  Win Hung ,  Kishimoto Ko

发明人： Chun-Chieh Lin ,  Wei-Hua Hsu ,  Yu-En Percy Chang ,  Chung Li Chang ,  Chi-Feng Cheng ,  Win Hung ,  Kishimoto Ko

IPC分类号： H01L29/94

CPC分类号： H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein the SiGe region has a first atomic percentage of germanium to germanium and silicon; and a silicide region over the SiGe region. The silicide region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is substantially lower than the first atomic percentage.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; SiGe区域，其中SiGe区域具有锗到锗和硅的第一原子百分比; 以及SiGe区域上的硅化物区域。 硅化物区域具有锗与锗和硅的第二原子百分比。 第二原子百分比基本上低于第一原子百分数。

公开(公告)号：US07423347B2

公开(公告)日：2008-09-09

申请号：US11334849

申请日：2006-01-19

申请人： Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

发明人： Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L21/2885 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.

摘要翻译： 提供了具有减小的小丘形成的半导体互连结构及其形成方法。 半导体互连结构包括形成在电介质层中的导体。 导体包括至少三个子层，其中相邻子层中杂质浓度的比优选大于约2。

公开(公告)号：US20070164439A1

公开(公告)日：2007-07-19

申请号：US11334849

申请日：2006-01-19

申请人： Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

发明人： Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

IPC分类号： H01L23/48

CPC分类号： H01L23/53238 ,  H01L21/2885 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.

摘要翻译： 提供了具有减小的小丘形成的半导体互连结构及其形成方法。 半导体互连结构包括形成在电介质层中的导体。 导体包括至少三个子层，其中相邻子层中杂质浓度的比优选大于约2。

公开(公告)号：US07235838B2

公开(公告)日：2007-06-26

申请号：US10881372

申请日：2004-06-30

申请人： Chun-Chieh Lin ,  Wen-Chin Lee

发明人： Chun-Chieh Lin ,  Wen-Chin Lee

IPC分类号： H01L27/108

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/10858 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/55 ,  H01L28/82

摘要： A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.

摘要翻译： 一种用于形成半导体器件的方法，该半导体器件包括具有嵌入式电容器结构的绝缘体上硅（SOI）衬底的DRAM单元结构，包括提供包括上覆的第一电绝缘层的衬底; 在所述第一电绝缘层上形成第一导电层以形成第一电极; 在所述第一电极上形成电容器电介质层; 在所述电容器介电层上形成第二导电层以形成第二电极; 在所述第二电极上形成第二电绝缘层; 以及在所述第二电极上形成单晶硅层以形成包括第一电容器结构的SOI衬底。

公开(公告)号：US07175709B2

公开(公告)日：2007-02-13

申请号：US10847099

申请日：2004-05-17

申请人： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

发明人： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC分类号： C30B25/04

CPC分类号： C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

摘要： A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

摘要翻译： 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US06963114B2

公开(公告)日：2005-11-08

申请号：US10749273

申请日：2003-12-29

申请人： Chun-Chieh Lin

发明人： Chun-Chieh Lin

IPC分类号： H01L29/41 ,  H01L21/02 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L27/1203 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66795 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic device including an insulator located over a substrate, a semiconductor feature and a contact layer. The semiconductor feature has a thickness over the insulator, a first surface opposite the insulator, and a sidewall spanning at least a portion of the thickness. The contact layer has a first member extending over at least a portion of the first surface and a second member spanning at least a portion of the sidewall.

摘要翻译： 包括位于衬底上的绝缘体，半导体特征和接触层的微电子器件。 半导体特征具有超过绝缘体的厚度，与绝缘体相对的第一表面和横跨至少一部分厚度的侧壁。 接触层具有在第一表面的至少一部分上延伸的第一构件和跨越侧壁的至少一部分的第二构件。