公开(公告)号：US08246027B2

公开(公告)日：2012-08-21

申请号：US12606112

申请日：2009-10-26

申请人： Shen-Chun Li ,  Shou-Kuo Hsu

发明人： Shen-Chun Li ,  Shou-Kuo Hsu

IPC分类号： B25B1/20 ,  B25B1/06 ,  B25B1/16 ,  B25B1/08 ,  B25B5/08 ,  B25B1/10 ,  B25B5/10 ,  B23Q3/18

CPC分类号： B25J15/026

摘要： A clamping apparatus includes a motor, a first cone gear secured to a shaft of the motor, and two clamping bodies attached to opposite sides of the motor. Each of the clamping bodies includes a second cone gear meshing with the first, a threaded post fixed to the second cone gear, a carriage threadedly connected with the threaded post, and a clamp arm fixed to the carriage. The motor rotates the first cone gear, and in turn the second cone gears and the corresponding threaded posts. With the rotation of the threaded posts, the carriages move towards or away from each other, whereby the clamp arms cooperatively acquire an object between the clamp arms, or release the object therefrom.

摘要翻译： 夹紧装置包括电动机，固定到电动机的轴的第一锥形齿轮和连接到电动机的相对侧的两个夹紧体。 每个夹紧体包括与第一锥形齿轮啮合的第二锥形齿轮，固定到第二锥形齿轮的螺纹柱，与螺纹柱螺纹连接的滑架和固定到滑架的夹紧臂。 电机旋转第一锥形齿轮，又旋转第二锥齿轮和相应的螺纹柱。 随着螺纹柱的旋转，滑架朝向或远离彼此移动，由此夹紧臂协同地获取夹紧臂之间的物体，或从其上释放物体。

公开(公告)号：US08194412B2

公开(公告)日：2012-06-05

申请号：US12647395

申请日：2009-12-25

申请人： Hua-Li Zhou ,  Chia-Nan Pai ,  Shou-Kuo Hsu

发明人： Hua-Li Zhou ,  Chia-Nan Pai ,  Shou-Kuo Hsu

IPC分类号： H05K1/18 ,  H05K1/16 ,  H05K7/00

CPC分类号： H05K1/0253 ,  H05K1/181 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10636 ,  Y02P70/611

摘要： A printed circuit board includes a signal plane and a reference plane. The signal plane includes a pad, a passive element mounted on the pad, and a signal transmission line electrically connected to the passive element via the pad. The reference plane provides a return path for a signal transmitted through the passive element and the signal transmission line. A void is defined in the reference plane corresponding to the passive element, to increase a length of the return path. A length of a first axis, perpendicular to the signal transmission line, of the void satisfies a following equation: W 1 ≈ 8 ⁢ Wpad + 10 ⁢ T 0.8 ⁢ Wtrace + T , wherein Wpad is a width of the pad, Wtrace is a width of the transmission line, T is the height of the pad.

摘要翻译： 印刷电路板包括信号平面和参考平面。 信号平面包括焊盘，安装在焊盘上的无源元件以及通过焊盘与无源元件电连接的信号传输线。 参考平面为通过无源元件和信号传输线传输的信号提供返回路径。 在对应于无源元件的参考平面中定义空隙，以增加返回路径的长度。 垂直于信号传输线的第一轴的长度满足以下等式：W 1≈8Wpad+ 10T 0.8Wtrace + T，其中Wpad是焊盘的宽度，Wtrace是 传输线的宽度，T是焊盘的高度。

公开(公告)号：US07817487B2

公开(公告)日：2010-10-19

申请号：US11952140

申请日：2007-12-07

申请人： Shou-Kuo Hsu ,  Duen-Yi Ho ,  Cheng-Shien Li

发明人： Shou-Kuo Hsu ,  Duen-Yi Ho ,  Cheng-Shien Li

IPC分类号： G11C5/14

CPC分类号： G06F1/26 ,  G11C5/04 ,  G11C5/147 ,  H05K1/0262 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09954 ,  H05K2201/10159

摘要： An exemplary motherboard includes a driving module, a first slot module arranged for mounting a first type of memory and connected to the driving module via a first channel, a second slot module arranged for mounting a second type of memory and connected to the driving module via a second channel, and a voltage regulator electronically connected to the first slot module and the second slot module. The first memory and the second memory are alternatively mounted on the motherboard, the voltage regulator detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of the memory mounted on the motherboard accordingly.

摘要翻译： 示例性主板包括驱动模块，布置成用于安装第一类型存储器并经由第一通道连接到驱动模块的第一插槽模块，布置成用于安装第二类型存储器并连接到驱动模块的第二插槽模块，其经由 第二通道和电连接到第一插槽模块和第二插槽模块的电压调节器。 第一存储器和第二存储器替代地安装在母板上，电压调节器检测当前安装在母板上的哪种类型的存储器，并相应地输出适合安装在母板上的存储器类型的电压。

公开(公告)号：US07599826B2

公开(公告)日：2009-10-06

申请号：US11309042

申请日：2006-06-13

申请人： Shou-Kuo Hsu ,  Cheng-Shien Li

发明人： Shou-Kuo Hsu ,  Cheng-Shien Li

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

摘要： A system for generating various simulation conditions for simulation analysis is disclosed. The system includes: a signal generating module (301) for generating an N-bit binary sequence consisting of “1” and “0” according to signal source parameters; a application module (302) for applying the N-bit binary sequence to generate the various simulation conditions according to control parameters; a noise generating module (303) for generating N influence values of Gauss noises with N standard deviations to N signal bit-widths; and an addition module (304) for adding the Gauss noises to corresponding digital waveform positions of the generated simulation conditions. A related method is also disclosed.

摘要翻译： 公开了一种用于生成用于模拟分析的各种模拟条件的系统。 该系统包括：根据信号源参数产生由“1”和“0”组成的N位二进制序列的信号产生模块（301） 应用模块（302），用于根据控制参数应用所述N位二进制序列以产生各种仿真条件; 噪声产生模块（303），用于产生具有N个标准偏差N个信号位宽的高斯噪声的N个影响值; 以及用于将高斯噪声加到所产生的模拟条件的相应数字波形位置的加法模块（304）。 还公开了相关方法。

公开(公告)号：US07596649B2

公开(公告)日：2009-09-29

申请号：US11759238

申请日：2007-06-07

申请人： Shou-Kuo Hsu ,  Cheng-Shien Li

发明人： Shou-Kuo Hsu ,  Cheng-Shien Li

IPC分类号： G06F13/00

CPC分类号： G06F13/4068 ,  G06F2213/0024 ,  H05K1/029 ,  H05K1/0295 ,  H05K2201/10363

摘要： A motherboard includes a chipset, a first connector pad suitable for receiving a first type of PCI connector, a second connector pad suitable for receiving a second type of PCI connector, a plurality of first transmission lines, a plurality of second transmission lines, and a plurality of areas for mounting switches. One end of each first transmission line is connected to the chipset, another end of each first transmission line is connected to an end of a corresponding area, one end of each second transmission line is connected to another end of the corresponding area, another end of each second transmission line is connected to the second connector pad, the first connector pad is connected to the plurality of first transmission lines, and the switches are selectively mounted on the plurality of areas.

摘要翻译： 主板包括芯片组，适于接收第一类型的PCI连接器的第一连接器焊盘，适于接收第二类型的PCI连接器的第二连接器焊盘，多个第一传输线，多条第二传输线，以及 多个安装开关的区域。 每个第一传输线的一端连接到芯片组，每个第一传输线的另一端连接到相应区域的一端，每个第二传输线的一端连接到相应区域的另一端，另一端 每个第二传输线连接到第二连接器焊盘，第一连接器焊盘连接到多个第一传输线，并且开关选择性地安装在多个区域上。

公开(公告)号：US07596460B2

公开(公告)日：2009-09-29

申请号：US11627378

申请日：2007-01-26

申请人： Duen-Yi Ho ,  Shou-Kuo Hsu

发明人： Duen-Yi Ho ,  Shou-Kuo Hsu

IPC分类号： G01R13/00

CPC分类号： G06F17/5036

摘要： A method for calculating a voltage spike value includes: predefining calculating requirements; inputting parameter values; analyzing whether inputted parameter values match with the calculating requirements; establishing a computing formula for calculating the voltage spike value if the inputted parameter values match with the calculating requirements; and calculating the voltage spike value by utilizing the inputted parameter values and the computing formula. A related system is also disclosed.

摘要翻译： 计算电压尖峰值的方法包括：预定义计算要求; 输入参数值; 分析输入的参数值是否符合计算要求; 如果输入的参数值与计算要求匹配，建立计算公式计算电压尖峰值; 以及通过利用输入的参数值和计算公式计算电压尖峰值。 还公开了相关系统。

公开(公告)号：US07530043B2

公开(公告)日：2009-05-05

申请号：US11563158

申请日：2006-11-25

申请人： Shou-Kuo Hsu ,  Cheng-Hong Liu

发明人： Shou-Kuo Hsu ,  Cheng-Hong Liu

IPC分类号： G06F17/50 ,  H05K7/08 ,  H05K1/11

CPC分类号： H05K1/0216 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09663

摘要： A printed circuit board includes a first layer including a first power portion and a first ground portion isolated from each other, and a second layer including a second power portion and a second ground portion isolated from each other. The second layer is spaced from the first layer. The second ground portion is arranged below the first power portion. The second power portion is arranged below the first ground portion. One portion of the first power portion overlaps one portion of the second power portion, and one portion of the first ground portion overlaps one portion of the second ground portion to provide a zero-intensity electric field between the first layer and the second layer. The first power portion is coupled to the second power portion via a first via. The first ground portion is coupled to the second ground portion via a second via.

摘要翻译： 印刷电路板包括第一层，第一层包括彼此隔离的第一电力部分和第一接地部分，以及包括彼此隔离的第二电力部分和第二接地部分的第二层。 第二层与第一层间隔开。 第二接地部分布置在第一电力部分的下方。 第二动力部分布置在第一接地部分的下方。 第一功率部分的一部分与第二功率部分的一部分重叠，并且第一接地部分的一部分与第二接地部分的一部分重叠，以在第一层和第二层之间提供零强度电场。 第一功率部分经由第一通孔耦合到第二功率部分。 第一接地部分经由第二通孔耦合到第二接地部分。

公开(公告)号：US07443265B2

公开(公告)日：2008-10-28

申请号：US11308690

申请日：2006-04-22

申请人： Shou-Kuo Hsu ,  Cheng-Hong Liu

发明人： Shou-Kuo Hsu ,  Cheng-Hong Liu

IPC分类号： H03H7/38

CPC分类号： H01P5/02 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for impedance matching between differential vias and associated transmission lines is provided. The method includes: deducing a relationship of a space between the differential vias, and a radius of the differential vias while a characteristic impedance of the differential vias matches a characteristic impedance of the differential transmission lines; and determining the space and the radius according to the relationship between the space and the radius.

摘要翻译： 提供了差分通孔和相关传输线之间的阻抗匹配方法。 该方法包括：当差分通孔的特性阻抗与差动传输线的特征阻抗匹配时，推断出差分通孔之间的空间与差动通路的半径之间的关系; 并根据空间和半径之间的关系确定空间和半径。

公开(公告)号：US20070220050A1

公开(公告)日：2007-09-20

申请号：US11525445

申请日：2006-09-22

申请人： Shou-Kuo Hsu ,  Chun-Jen Chen ,  Chun-Shan Hsiao

发明人： Shou-Kuo Hsu ,  Chun-Jen Chen ,  Chun-Shan Hsiao

IPC分类号： G06F17/00

CPC分类号： H03H1/0007 ,  H03H2260/00

摘要： A method for selecting a ferrite bead for a filter to avoid a peak value in a frequency response curve of the filter is provided. The method includes the steps of: building an equivalent model database including parameters of equivalent models of ferrite beads, the parameters including an inductance and a capacitance of a corresponding equivalent model of each ferrite bead; calculating parameters of a desired ferrite bead in the filter based on parameters of the filter, the parameters of the ferrite bead including an inductance, a capacitance, and a resonant frequency; adjusting parameters of the filter until the calculated resonant frequency equals or approaches a desired resonant frequency, and finding an inductance and a capacitance respectively equaling or approaching the calculated inductance and the calculated capacitance in the database; and selecting a ferrite bead with the appropriate inductance and capacitance as found in the database for the filter.

摘要翻译： 提供了一种用于选择用于滤波器的铁氧体磁珠以避免滤波器的频率响应曲线中的峰值的方法。 该方法包括以下步骤：构建等效模型数据库，其中包括铁素体磁珠的等效模型参数，其参数包括每个铁氧体磁珠的相应等效模型的电感和电容; 基于滤波器的参数，包括电感，电容和谐振频率的铁氧体磁珠的参数来计算滤波器中期望的铁氧体磁珠的参数; 调整滤波器的参数，直到计算出的谐振频率等于或接近期望的谐振频率，并且找到分别等于或接近计算出的电感的电感和电容以及数据库中的计算电容; 并选择具有适当的电感和电容的铁氧体磁珠，如过滤器数据库中所述。

公开(公告)号：US20060045226A1

公开(公告)日：2006-03-02

申请号：US11212338

申请日：2005-08-26

申请人： Cheng-Shien Li ,  Shou-Kuo Hsu

发明人： Cheng-Shien Li ,  Shou-Kuo Hsu

IPC分类号： G06F19/00

CPC分类号： G06F17/5036 ,  G01R31/31709

摘要： The present invention provides a system and a method for analyzing jitter of various signals including measurement signals and simulation signals. The method includes the steps of: (a) obtaining a signal file; (b) identifying a type of the signal file; (c) defining a jitter analysis mode from a phase jitter mode, a periodic jitter mode and a cycle jitter mode; (d) obtaining an n-bit differential signal from the signal file; (e) rebuilding an ideal clock based on the differential signal by means of performing a Minimum Deviation Algorithm (MDA); (f) calculating and analyzing jitter of the differential signal according to the ideal clock by means of performing the MDA; and (g) generating and outputting a jitter analysis wave and jitter analysis results according to the defined jitter analysis mode.