公开(公告)号：US08441327B2

公开(公告)日：2013-05-14

申请号：US12960321

申请日：2010-12-03

申请人： Hua-Li Zhou ,  Ming Wei ,  Chia-Nan Pai ,  Shou-Kuo Hsu

发明人： Hua-Li Zhou ,  Ming Wei ,  Chia-Nan Pai ,  Shou-Kuo Hsu

IPC分类号： H03H7/38

CPC分类号： H05K1/0245 ,  H05K2201/09727

摘要： A printed circuit board includes an insulation layer and a signal layer attached to the insulation layer. The signal layer includes a pair of differential transmission lines. Width W of each of the differential transmission lines is changed according to change of space S between the differential transmission lines, based on the following formula: W = C ⁢ ⁢ 1 × H × ( C ⁢ ⁢ 2 × H 0.8 ⁢ W 0 + T ) C ⁢ ⁢ 3 × ⅇ C ⁢ ⁢ 4 × S 0 H - 1 1 - C ⁢ ⁢ 3 × ⅇ C ⁢ ⁢ 4 × S H - 1.25 ⁢ T In above formula, C1=7.475, C2=5.98, C3=0.48, C4=−0.96, H is a thickness of the insulation layer, W0 is an original width of each of the differential transmission lines, and S0 is an original space between the differential transmission lines, and T is a thickness of each of the differential transmission lines.

摘要翻译： 印刷电路板包括绝缘层和附着到绝缘层的信号层。 信号层包括一对差动传输线。 差分传输线路的宽度W根据以下公式根据差分传输线路之间的空间S的变化而变化：W = C⁢1×H×（Cé2×H 0.8W 0 + T）C uch 3×ⅇC ud 4×S 0 H-1 1 -C⁢3×ⅇC ud 4×SH-1.25T在上式中，C1 = 7.475，C2 = 5.98，C3 = 0.48，C4 = -0.96，H是绝缘层的厚度，W0是差分传输线的原始宽度，S0是差动传输线之间的原始空间，T是各个差分传输线的厚度 差动传输线。

公开(公告)号：US08194412B2

公开(公告)日：2012-06-05

申请号：US12647395

申请日：2009-12-25

申请人： Hua-Li Zhou ,  Chia-Nan Pai ,  Shou-Kuo Hsu

发明人： Hua-Li Zhou ,  Chia-Nan Pai ,  Shou-Kuo Hsu

IPC分类号： H05K1/18 ,  H05K1/16 ,  H05K7/00

CPC分类号： H05K1/0253 ,  H05K1/181 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10636 ,  Y02P70/611

摘要： A printed circuit board includes a signal plane and a reference plane. The signal plane includes a pad, a passive element mounted on the pad, and a signal transmission line electrically connected to the passive element via the pad. The reference plane provides a return path for a signal transmitted through the passive element and the signal transmission line. A void is defined in the reference plane corresponding to the passive element, to increase a length of the return path. A length of a first axis, perpendicular to the signal transmission line, of the void satisfies a following equation: W 1 ≈ 8 ⁢ Wpad + 10 ⁢ T 0.8 ⁢ Wtrace + T , wherein Wpad is a width of the pad, Wtrace is a width of the transmission line, T is the height of the pad.

摘要翻译： 印刷电路板包括信号平面和参考平面。 信号平面包括焊盘，安装在焊盘上的无源元件以及通过焊盘与无源元件电连接的信号传输线。 参考平面为通过无源元件和信号传输线传输的信号提供返回路径。 在对应于无源元件的参考平面中定义空隙，以增加返回路径的长度。 垂直于信号传输线的第一轴的长度满足以下等式：W 1≈8Wpad+ 10T 0.8Wtrace + T，其中Wpad是焊盘的宽度，Wtrace是 传输线的宽度，T是焊盘的高度。

公开(公告)号：US08633401B2

公开(公告)日：2014-01-21

申请号：US13217626

申请日：2011-08-25

申请人： Hua-Li Zhou ,  Chia-Nan Pai ,  Shou-Kuo Hsu

发明人： Hua-Li Zhou ,  Chia-Nan Pai ,  Shou-Kuo Hsu

IPC分类号： H05K1/11

CPC分类号： H05K1/111 ,  H05K1/0242 ,  H05K1/025 ,  H05K2201/09736 ,  Y02P70/611

摘要： A pad includes a first mating section and a second mating section. The first mating section includes a first horizontal plane and a first inclined plane. The second mating section includes a second horizontal plane and a second inclined plane. The first mating section is a copper foil capable of being connected to a wire. The second mating section is made of insulating material. The first inclined plane and the second inclined plane are bonded together.

摘要翻译： 垫包括第一配合部分和第二配合部分。 第一配合部分包括第一水平面和第一倾斜平面。 第二配合部分包括第二水平面和第二倾斜平面。 第一配合部分是能够连接到电线的铜箔。 第二配合部分由绝缘材料制成。 第一倾斜平面和第二倾斜平面结合在一起。

公开(公告)号：US08604351B2

公开(公告)日：2013-12-10

申请号：US13335996

申请日：2011-12-23

申请人： Hua-Li Zhou ,  Chia-Nan Pai ,  Shou-Kuo Hsu

发明人： Hua-Li Zhou ,  Chia-Nan Pai ,  Shou-Kuo Hsu

IPC分类号： H05K1/09

CPC分类号： H05K1/0253

摘要： A printed circuit board includes a signal layer and a reference layer. The signal layer is covered with copper foil. A circuit topology for multiple loads is set on the signal layer. The circuit topology includes a driving terminal, a first signal receiving terminal, and a second signal receiving terminal. The driving terminal is connected to a node through a first transmission line. The node is connected to the first and second signal receiving terminals respectively through a second and a third transmission lines. A difference between lengths of the second and third transmission lines is greater than a product of a transmission speed and a rise time of signals from the driving terminal. The reference layer is covered with copper foil, and arranged under the signal layer. A region without copper foil is formed on the reference layer, under the second transmission line.

摘要翻译： 印刷电路板包括信号层和参考层。 信号层被铜箔覆盖。 在信号层上设置多个负载的电路拓扑。 电路拓扑包括驱动端子，第一信号接收端子和第二信号接收端子。 驱动终端通过第一传输线连接到节点。 节点分别通过第二和第三传输线连接到第一和第二信号接收终端。 第二和第三传输线的长度之差大于来自驱动终端的信号的传输速度和上升时间的乘积。 参考层用铜箔覆盖，并布置在信号层下面。 在第二传输线下方，在参考层上形成没有铜箔的区域。

公开(公告)号：US08402423B2

公开(公告)日：2013-03-19

申请号：US13244625

申请日：2011-09-25

申请人： Zheng Shan ,  Shi-Piao Luo ,  Chia-Nan Pai ,  Shou-Kuo Hsu

发明人： Zheng Shan ,  Shi-Piao Luo ,  Chia-Nan Pai ,  Shou-Kuo Hsu

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5077

摘要： In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance.

摘要翻译： 在使用计算装置验证印刷电路板（PCB）布局的方法中，从计算装置的存储装置获得PCB模拟文件，并且根据PCB仿真文件在显示装置上显示PCB图像。 PCB图像包括多个信号线和开关电压调节器节点（SVRN）。 从PCB图像中选择要检查的SVRN，并搜索SVRN周围的所有信号线。 该方法计算所选择的SVRN与所搜索的信号线之间的布局距离，并且生成图形窗口界面以定位其布局距离等于或小于最小距离的信号线。 该方法通过将布局距离增加到最小距离来进一步修改定位信号线的布局以满足布局设计规范。

公开(公告)号：US08247704B2

公开(公告)日：2012-08-21

申请号：US12503680

申请日：2009-07-15

申请人： Chia-Nan Pai ,  Han-Long Chen ,  Ning Li ,  Shou-Kuo Hsu

发明人： Chia-Nan Pai ,  Han-Long Chen ,  Ning Li ,  Shou-Kuo Hsu

IPC分类号： H05K1/18 ,  H05K3/30

CPC分类号： H05K1/0239 ,  H05K1/0245 ,  H05K1/0295 ,  H05K1/113 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10015 ,  H05K2201/10545 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913

摘要： A motherboard interconnection device includes a top layer, a bottom layer, a first and a third electronic elements positioned on the top layer, and a second and a fourth electronic elements positioned on the bottom layer. A first end of the first electronic element on the top layer is connected to the first end of the second electronic element on the bottom layer with a first via hole, and the first end of the third electronic element on the top layer is connected to the first end of the fourth electronic element on the bottom layer with a second via hole. The second ends of the two electronic elements on the top layer are connected to a first part, and the second ends of the two electronic elements on the bottom layer are connected to a second part.

摘要翻译： 母板互连装置包括顶层，底层，位于顶层上的第一和第三电子元件以及位于底层上的第二和第四电子元件。 顶层上的第一电子元件的第一端通过第一通孔连接到底层上的第二电子元件的第一端，并且顶层上的第三电子元件的第一端连接到 第四电子元件的第一端部具有第二通孔。 顶层上的两个电子元件的第二端连接到第一部分，底层上的两个电子元件的第二端连接到第二部分。

公开(公告)号：US08058557B2

公开(公告)日：2011-11-15

申请号：US11957416

申请日：2007-12-15

申请人： Chien-Hung Liu ,  Shou-Kuo Hsu ,  Chia-Nan Pai

发明人： Chien-Hung Liu ,  Shou-Kuo Hsu ,  Chia-Nan Pai

IPC分类号： H05K1/00

CPC分类号： H05K1/0245 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672

摘要： An exemplary PCB includes a first reference layer, a first signal layer, a second signal layer, and a third signal layer in that order, a first differential pair is arranged in the first signal layer in edge-coupled structure and references the first reference layer, a distance between the first signal layer and the second signal layer is greater than a distance between the first reference layer and the first signal layer, a second differential pair is arranged in the second signal layer and the third signal layer in broad-coupled structure. The PCB has a high density layout of transmission lines.

摘要翻译： 示例性PCB包括第一参考层，第一信号层，第二信号层和第三信号层，第一差分对以边缘耦合结构布置在第一信号层中，并参考第一参考层 第一信号层和第二信号层之间的距离大于第一参考层和第一信号层之间的距离，第二差分对被布置在第二信号层中，第三信号层以广泛耦合结构 。 PCB具有传输线高密度布局。

公开(公告)号：US08510705B2

公开(公告)日：2013-08-13

申请号：US13327771

申请日：2011-12-16

申请人： Jia-Lu Ye ,  Chia-Nan Pai ,  Shou-Kuo Hsu

发明人： Jia-Lu Ye ,  Chia-Nan Pai ,  Shou-Kuo Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A computer-based method and a computing device for checking stub lengths of via stubs of a printed circuit board (PCB) layout are provided. The computing device displays a check interface, selects signal transmission line from a currently run PCB layout through the check interface, receives a reference stub length input through the check interface, and determines the actual stub length of each via stub of each via each selected signal transmission line connected to. The computing device further determines that a design of one via stub satisfies the design standards, if the actual stub length of the one stub via is less than or equal to the reference length, and determines that a design of one via stub does not satisfy the design standards if the actual stub length of the one via stub is greater than the reference stub length.

摘要翻译： 提供了一种基于计算机的方法和用于检查印刷电路板（PCB）布局的通孔短截线的短截线长度的计算装置。 计算装置显示检查接口，通过检查接口从当前运行的PCB布局中选择信号传输线，接收通过检查接口输入的参考短截线长度，并通过每个选定信号确定每个通孔短截线的实际短截线长度 传输线连接。 如果一个存根通孔的实际短截线长度小于或等于参考长度，则计算设备还确定一个通孔存根的设计满足设计标准，并且确定一个通孔存储体的设计不满足 如果一个通过存根的实际存根长度大于参考短截线长度，则设计标准。

公开(公告)号：US08383957B2

公开(公告)日：2013-02-26

申请号：US12875156

申请日：2010-09-03

申请人： Shou-Kuo Hsu ,  Yung-Chieh Chen ,  Hsien-Chuan Liang ,  Wen-Laing Tseng ,  Shen-Chun Li ,  Chia-Nan Pai

发明人： Shou-Kuo Hsu ,  Yung-Chieh Chen ,  Hsien-Chuan Liang ,  Wen-Laing Tseng ,  Shen-Chun Li ,  Chia-Nan Pai

IPC分类号： H05K1/11

CPC分类号： H05K1/0251 ,  H05K1/115 ,  H05K2201/09836 ,  Y10T428/24917

摘要： A printed circuit board (PCB) includes two layers, two signal transmission traces, and a vertical interconnect access (via). The signal transmission traces are respectively arranged on the layers. The signal transmission traces are electrically connected to each other through the via. A centerline of the via with a vertical line of the layers form an acute angle θ, the angle θ is less than cos−1[(Lv2−Lt2)/(Lv2+Lt2)]. Wherein Lt is loss of the two signal transmitting traces in a unit length, and Lv is loss of the via in a unit length.

摘要翻译： 印刷电路板（PCB）包括两层，两条信号传输路径和一条垂直互连接口（via）。 信号传输迹线分别布置在层上。 信号传输迹线通过通孔彼此电连接。 具有垂直线的通孔的中心线形成锐角和角度;角度和角度; 小于cos-1 [（Lv2-Lt2）/（Lv2 + Lt2）]。 其中Lt是以单位长度丢失两个信号传输迹线，并且Lv是单位长度中的通孔的损失。

公开(公告)号：US08110747B2

公开(公告)日：2012-02-07

申请号：US12430133

申请日：2009-04-27

申请人： Shou-Kuo Hsu ,  Chia-Nan Pai

发明人： Shou-Kuo Hsu ,  Chia-Nan Pai

IPC分类号： H05K1/00

CPC分类号： H05K1/0245 ,  H05K1/0253 ,  H05K1/0393 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0969

摘要： A flexible printed circuit board (FPCB) includes a signal layer, upper and lower ground layers, and two dielectric layers. The signal layer includes a differential pair comprising two transmission lines to transmit a pair of differential signals. The dielectric layers are located on and under the signal layer to sandwich the signal layer. The upper ground layer is attached to the dielectric layer on the signal layer, opposite to the signal layer. The lower ground layer is attached to the dielectric layer under the signal layer, opposite to the signal layer. Each ground layer includes a grounded sheet made of conductive material. Two voids are defined in each ground layer and located at opposite sides of the corresponding grounded sheet. Distances between the middle line of the grounded sheet of each ground layer and middle lines of the two transmission lines are equal.

摘要翻译： 柔性印刷电路板（FPCB）包括信号层，上下接地层和两个电介质层。 信号层包括差分对，该差分对包括用于发送一对差分信号的两条传输线。 电介质层位于信号层之上和之下，以夹住信号层。 上层接地层与信号层的电介质层相连，与信号层相反。 下部接地层附着在与信号层相反的信号层下面的电介质层上。 每个接地层包括由导电材料制成的接地片。 在每个接地层中定义两个空隙，并且位于相应接地片的相对侧。 每个接地层的接地片的中间线与两条传输线的中间线之间的距离相等。