公开(公告)号：US06867428B1

公开(公告)日：2005-03-15

申请号：US10282712

申请日：2002-10-29

申请人： Paul R. Besser ,  Eric N. Paton ,  Qi Xiang

发明人： Paul R. Besser ,  Eric N. Paton ,  Qi Xiang

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/6659 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

摘要： An n-type strained silicon MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon regions are provided in the silicon geranium layer at opposing sides of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon regions. By forming the shallow source and drain extensions in silicon regions rather than in silicon germanium, source and drain extension distortions caused by the enhanced diffusion rate of arsenic in silicon germanium are avoided.

摘要翻译： n型应变硅MOSFET利用形成在硅锗衬底上的应变硅沟道区。 在应变硅沟道区的相对侧的硅天竺塔层中设置有硅区，并且在硅区域中注入浅的源极和漏极延伸。 通过在硅区域而不是在硅锗中形成浅的源极和漏极延伸部分，避免了由锗在锗中增加的扩散速率引起的源极和漏极扩展失真。

公开(公告)号：US06642590B1

公开(公告)日：2003-11-04

申请号：US09691227

申请日：2000-10-19

申请人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

发明人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

IPC分类号： H01L2976

CPC分类号： H01L29/4941 ,  H01L21/2807

摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. A barrier layer is deposited on the PVD amorphous silicon layer. The metal is then formed on the barrier layer. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer. The barrier layer prevents interaction between the PVD amorphous silicon layer and the metal, thereby allowing higher temperature subsequent processing while preserving the work function of the gate.

摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 栅极在衬底上包括高介电常数，以及在高k栅极电介质上的非晶硅的物理气相沉积（PVD）层。 阻挡层沉积在PVD非晶硅层上。 然后在阻挡层上形成金属。 由于PVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。 阻挡层防止PVD非晶硅层和金属之间的相互作用，从而允许更高温度的后续处理，同时保持栅极的功函数。

公开(公告)号：US06611576B1

公开(公告)日：2003-08-26

申请号：US09780476

申请日：2001-02-12

申请人： Paul R. Besser ,  Paul L. King

发明人： Paul R. Besser ,  Paul L. King

IPC分类号： G01N23223

CPC分类号： C23C14/545 ,  G01N23/223 ,  G01N2223/076

摘要： A novel method of automatically controlling thickness of a metal film during film deposition in a deposition chamber. The method involves producing an X-ray beam directed to the metal film deposited on a wafer in a deposition chamber, and detecting X-ray fluorescence of the metal film. The thickness of the metal film determined based on the detected X-ray fluorescence is compared with a preset value to continue deposition if the determined thickness is less than the preset value. Deposition is stopped when the determined thickness reaches the preset value.

摘要翻译： 一种在淀积室中成膜期间自动控制金属膜厚度的新方法。 该方法包括产生指向沉积在沉积室中的晶片上的金属膜的X射线束，并且检测金属膜的X射线荧光。 如果确定的厚度小于预设值，则将基于检测到的X射线荧光确定的金属膜的厚度与预设值进行比较以继续沉积。 当确定的厚度达到预设值时，停止沉积。

公开(公告)号：US06528362B1

公开(公告)日：2003-03-04

申请号：US09691181

申请日：2000-10-19

申请人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

发明人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L21/28061 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/66545

摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the CVD amorphous silicon layer. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.

摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。 然后在CVD非晶硅层上形成金属。 由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

公开(公告)号：US06518154B1

公开(公告)日：2003-02-11

申请号：US09813310

申请日：2001-03-21

申请人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

发明人： Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser

IPC分类号： H01L213205

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/823842 ,  H01L29/4975

摘要： MOS transistors and CMOS devices comprising a plurality of transistors including metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal on a thin gate insulator layer extending over first and second active device (e.g., a MOS transistor) precursor regions of a semiconductor substrate; selectively forming at least one masking layer segment on the first blanket layer overlying selective ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or semi-metal, or silicon, over the thus-formed structure; effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying the other ones of the transistor precursor regions; exposing and selectively removing the masking layer segment; and simultaneously patterning the alloyed and unalloyed/unsilicided portions of the first blanket layer to form metal-based gate electrodes of different composition. The invention also includes MOS and CMOS devices comprising differently composed metal-based gate electrodes.

摘要翻译： 包括多个晶体管的MOS晶体管和CMOS器件包括不同组成的金属基栅极，其方法包括：在第一和第二有源器件上延伸的薄栅极绝缘层上沉积第一金属的第一覆盖层（例如， ，MOS晶体管）前驱体区域; 选择性地形成覆盖所述MOS晶体管前体区域中的选择性掩模层的所述第一覆盖层上的至少一个掩模层段; 在如此形成的结构上沉积第二金属或半金属或硅的第二覆盖层; 在覆盖晶体管前体区域中的另一层的第一和第二覆盖层的接触部分之间发生合金化或硅化反应; 曝光和选择性地去除掩模层段; 并且同时对第一覆盖层的合金化和非合金化/未硅化部分进行构图，以形成不同组成的金属基栅电极。 本发明还包括包含不同组合的金属基栅极的MOS和CMOS器件。

公开(公告)号：US06514858B1

公开(公告)日：2003-02-04

申请号：US09829202

申请日：2001-04-09

申请人： Frederick N. Hause ,  Paul R. Besser ,  Frank Mauersberger ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

发明人： Frederick N. Hause ,  Paul R. Besser ,  Frank Mauersberger ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

IPC分类号： H01L214763

CPC分类号： H01L22/34 ,  B24B37/042 ,  B24B49/00 ,  H01L21/31053 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.

摘要翻译： 提供了一种用于控制半导体器件的抛光工艺的测试结构。 测试结构由结构层，第一处理层和互连构成。 第一处理层位于结构层上方，并且具有形成在其中并且至少部分地穿过其延伸到预选深度的多个开口。 多个开口的至少一部分具有在从第一处理层朝向结构层的方向上逐渐变窄的锥形区域。 开口间隔开预定距离X. 互连形成在包括锥形区域的多个开口中。 因此，当通过抛光工艺去除工艺层和互连件时，距离X增加，表示抛光过程的深度。

公开(公告)号：US06444513B1

公开(公告)日：2002-09-03

申请号：US09810348

申请日：2001-03-19

申请人： Paul R. Besser ,  Srikanteswara Dakshina-Murthy

发明人： Paul R. Besser ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L218238

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  Y10S438/947 ,  Y10S438/949

摘要： A metal gate structure and method of forming the same introduces metal impurities into a first metal layer, made of TiN, for example. The impurities create a surface region of greater etch selectivity that prevents overetching of the TiN during the etching of an overlying tungsten gate during the formation of the metal gate structure. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum as the metal impurities provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.

摘要翻译： 金属栅结构及其形成方法将金属杂质引入例如由TiN制成的第一金属层中。 这些杂质产生更大的蚀刻选择性的表面区域，其防止了在形成金属栅极结构期间在覆盖钨栅的蚀刻过程中TiN的过蚀刻。 防止TiN的过蚀刻保护栅极氧化物免受不希望的退化。 提供铝或钽作为金属杂质提供了足够的蚀刻停止能力，并且不会不希望地影响TiN的功函数。

公开(公告)号：US06406993B1

公开(公告)日：2002-06-18

申请号：US09523439

申请日：2000-03-10

申请人： Srikanteswara Dakshina-Murthy ,  Paul R. Besser ,  Jonathan B. Smith ,  Eric M. Apelgren ,  Christian Zistl ,  Jeremy I. Martin ,  Lie Larry Zhao ,  Nicholas J. Kepler

发明人： Srikanteswara Dakshina-Murthy ,  Paul R. Besser ,  Jonathan B. Smith ,  Eric M. Apelgren ,  Christian Zistl ,  Jeremy I. Martin ,  Lie Larry Zhao ,  Nicholas J. Kepler

IPC分类号： H01L214763

CPC分类号： H01L21/76816 ,  H01L21/76831

摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an opening in the hard mask layer. The method further comprises forming a sidewall spacer in the opening in the hard mask layer that defines a reduced opening, forming an opening in the layer of dielectric material below the reduced opening, and forming a conductive interconnection in the opening in the dielectric layer.

摘要翻译： 本发明涉及一种形成半导体器件的方法。 在一个说明性实施例中，该方法包括形成电介质材料层，在介电材料层之上形成硬掩模层，并在硬掩模层中形成开口。 所述方法还包括在所述硬掩模层中的所述开口中形成侧壁间隔物，所述开口限定缩小的开口，在所述还原开口下方的介电材料层中形成开口，以及在所述电介质层的所述开口中形成导电互连。

公开(公告)号：US06368950B1

公开(公告)日：2002-04-09

申请号：US09734186

申请日：2000-12-12

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L213205

CPC分类号： H01L29/66545 ,  H01L21/28097

摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.

摘要翻译： 实现自对准金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆金属相互作用以形成自对准金属硅化物栅极来实现的。 在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。 除了凹部中硅的部分之外，除去硅。 通过操纵金属和自对准金属硅化物栅之间的蚀刻选择性来去除金属的剩余部分。

公开(公告)号：US06342414B1

公开(公告)日：2002-01-29

申请号：US09734189

申请日：2000-12-12

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L218238

CPC分类号： H01L21/28194 ,  H01L21/28097 ,  H01L21/28114 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

摘要翻译： 实现自对准低温金属硅化物栅极的方法是通过将低温硅化金属限制在覆盖沟道的凹槽内并进行退火以使低温硅化金属及其上覆的硅相互作用以形成自对准低 温度金属硅化物门。 进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。