公开(公告)号：US6162681A

公开(公告)日：2000-12-19

申请号：US346042

申请日：1999-07-06

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L27/10817 ,  H01L27/10852

Abstract: A method for forming a fork-shaped capacitor of a dynamic random access memory cell is disclosed. The method includes forming a first conductive layer (118) over a semiconductor substrate (110), wherein at least a portion of the first doped polysilicon layer communicates to the substrate. A first dielectric layer is formed on the first conductive layer and is then patterned to form an opening therein and expose a portion of the first conductive layer. A second conductive layer is formed on the sidewall of the first dielectric layer and the exposed portion of the first conductive layer. A second dielectric spacer is formed on the sidewall of the second conductive layer. The first conductive layer is etched using the second dielectric layer as a mask, and a third conductive spacer is formed on the sidewalls of the second dielectric spacer. The second dielectric layer are then removed. Finally, a third dielectric layer and a fourth conductive layer are formed in turn on the first, the second, and the third conductive layers.

Abstract translation: 公开了一种用于形成动态随机存取存储器单元的叉形电容器的方法。 该方法包括在半导体衬底（110）上形成第一导电层（118），其中第一掺杂多晶硅层的至少一部分与衬底连通。 第一电介质层形成在第一导电层上，然后被图案化以在其中形成开口，并露出第一导电层的一部分。 第二导电层形成在第一介电层的侧壁和第一导电层的暴露部分上。 在第二导电层的侧壁上形成第二电介质隔离物。 使用第二介电层作为掩模来蚀刻第一导电层，并且在第二电介质间隔物的侧壁上形成第三导电间隔物。 然后去除第二电介质层。 最后，依次在第一，第二和第三导电层上形成第三电介质层和第四导电层。

公开(公告)号：US6153467A

公开(公告)日：2000-11-28

申请号：US271736

申请日：1999-03-18

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method of fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect is disclosed. The method comprises following steps. Firstly, a pad oxide layer and a conductive impurity (such as phosphorus) doped polysilicon layer is successively formed on the silicon substrate. Then, an oxidation process is performed to oxidize the polysilicon layer and to drive in the conductive impurities. After coating a patterned mask on the resultant surface to define a plurality of buried bit line regions, a dry etch is used to etch away the unmask regions till the silicon substrate is slightly recessed to form shallow trenches. Subsequently, the photoresist is stripped, and a gate dielectric layer, such as gate nitride or oxynitride layer is formed on the resultant surface. After refilling a plurality of trenches with a conductive impurity doped silicon layer, a planarization process such as CMP is followed to form a plain surface using the gate dielectric layer as an etching stopped layer. A stacked ONO layer is then deposited as an interpoly dielectric layer; and finally another a conductive impurity doped polysilicon layer is formed and patterned to be as word lines.

Abstract translation: 公开了一种利用浅沟槽浮动栅极制造掩埋位线闪光EEROM的方法，用于抑制短沟道效应。 该方法包括以下步骤。 首先，在硅衬底上依次形成衬垫氧化物层和导电杂质（例如磷）掺杂多晶硅层。 然后，进行氧化处理以氧化多晶硅层并驱动导电杂质。 在所得表面上涂覆图案化掩模以限定多个掩埋位线区域之后，使用干蚀刻来蚀刻去除掩模区域，直到硅衬底稍微凹入以形成浅沟槽。 随后，剥离光致抗蚀剂，并且在所得表面上形成诸如栅极氮化物或氧氮化物层的栅极电介质层。 在用导电杂质掺杂硅层重新填充多个沟槽之后，使用诸如CMP的平坦化工艺，使用栅极介电层作为蚀刻停止层来形成平坦表面。 堆叠的ONO层随后沉积为互聚电介质层; 并且最后形成另一个导电杂质掺杂多晶硅层并将其图案化为字线。

公开(公告)号：US6146949A

公开(公告)日：2000-11-14

申请号：US104532

申请日：1998-06-25

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8246

CPC classification number: H01L27/1126

Abstract: A method for forming mask read-only memories comprises: A gate oxide layer is formed on a semiconductor substrate. A polysilicon layer is formed on the gate oxide layer. Then, a silicon nitride layer is formed on said polysilicon layer. The gate structures are defined by patterning the silicon nitride layer and the polysilicon layer. Subsequently, the silicon oxide spacers are formed on the sidewalls of the gate structures. An ion implantation is performed to form the buried bit lines in said semiconductor substrate between said gate structures. A BPSG layer is formed on said semiconductor substrate. Then, the BPSG layer is polished until the top surface of said gate structures and the silicon nitride layer is removed. A conductive layer is formed along the surfaces of said residual BPSG layer, silicon oxide spacers and polysilicon layer.

Abstract translation: 用于形成掩模只读存储器的方法包括：在半导体衬底上形成栅氧化层。 在栅氧化层上形成多晶硅层。 然后，在所述多晶硅层上形成氮化硅层。 栅极结构通过图案化氮化硅层和多晶硅层来限定。 随后，在栅结构的侧壁上形成氧化硅间隔物。 执行离子注入以在所述栅极结构之间的所述半导体衬底中形成掩埋位线。 在所述半导体衬底上形成BPSG层。 然后，抛光BPSG层直到去除所述栅结构的顶表面和氮化硅层。 沿着所述残留BPSG层，氧化硅间隔物和多晶硅层的表面形成导电层。

公开(公告)号：US6137131A

公开(公告)日：2000-10-24

申请号：US999449

申请日：1997-12-29

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/68 ,  H01L27/00

CPC classification number: H01L28/82 ,  H01L28/92 ,  H01L27/10814 ,  H01L27/10852

Abstract: The capacitor includes a first storage node formed over a semiconductor wafer. The first storage node has a plurality of mushroom-shape structures. The plurality of mushroom-shape structures are randomly arranged on the first storage node to increase the area of the first storage node. A dielectric layer conformally covers the first storage node. A second storage node is formed on the dielectric layer.

Abstract translation: 电容器包括形成在半导体晶片上的第一存储节点。 第一存储节点具有多个蘑菇形结构。 多个伞形结构被随机地布置在第一存储节点上以增加第一存储节点的面积。 电介质层共形地覆盖第一存储节点。 第二存储节点形成在电介质层上。

公开(公告)号：US06133104A

公开(公告)日：2000-10-17

申请号：US323772

申请日：1999-06-01

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L21/425 ,  H01L21/336

CPC classification number: H01L21/28525 ,  H01L21/76895 ,  H01L27/11

Abstract: The method of forming buried contacts on a semiconductor substrate is as follows. At first, a gate insulator layer is formed on the substrate. An undoped silicon layer is then formed on the substrate, and a dielectric layer is formed on the undoped silicon layer. Portions of the dielectric layer, of the undoped silicon layer, and of the gate insulator layer are removed to define a buried contact opening. A doping step is carried out to dope the substrate for forming a buried contact region. A doped silicon layer is formed over the substrate. Next, a portion of the doped silicon layer is then removed to leave a silicon connection and a doped silicon sidewall. The dielectric layer is removed and a thermal oxidization is performed to form a thermal oxide layer on the exposed silicon surfaces. A gate region is defined by removing portions of the thermal oxide layer and the undoped silicon layer. The substrate is doped for forming a lightly doped source/drain region. Dielectric sidewalls are then formed on sidewalls of the gate region and of the doped silicon sidewall. Finally, the substrate is doped to form a source/drain region in the substrate under an exposed region of the substrate.

Abstract translation: 在半导体基板上形成埋入触点的方法如下。 首先，在基板上形成栅极绝缘体层。 然后在衬底上形成未掺杂的硅层，并且在未掺杂的硅层上形成电介质层。 介质层，未掺杂的硅层和栅极绝缘体层的部分被去除以限定掩埋的接触开口。 进行掺杂步骤以掺杂用于形成掩埋接触区域的衬底。 在衬底上形成掺杂硅层。 接下来，然后去除掺杂硅层的一部分以留下硅连接和掺杂的硅侧壁。 去除介电层，并进行热氧化，以在暴露的硅表面上形成热氧化层。 通过去除热氧化物层和未掺杂的硅层的部分来限定栅极区域。 掺杂衬底以形成轻掺杂的源/漏区。 然后在栅极区域和掺杂硅侧壁的侧壁上形成介质侧壁。 最后，衬底被掺杂以在衬底的衬底的暴露区域之下形成源极/漏极区域。

公开(公告)号：US6127706A

公开(公告)日：2000-10-03

申请号：US65323

申请日：1998-04-23

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/11 ,  H01L21/28525 ,  H01L21/76895

Abstract: A buried contact structure on a semiconductor substrate in the present invention is as follows. A gate insulator is on a portion of the substrate and a gate electrode is located over the gate insulator. A gate sidewall structure is on the sidewall of the gate electrode. A lightly doped junction region in the substrate is under the gate sidewall structure. A doped junction region is in the substrate abutting the lightly doped junction region and is located aside from the gate insulator. A doped buried contact region is in the substrate next to the doped junction region. An interconnect is located over a first portion of the doped buried contact region.The buried contact structure can further include a shielding layer over a second portion of the doped buried contact region. For forming more connections, the buried contact structure can further have a dielectric layer over the interconnect, the substrate, the gate sidewall structure, and the gate electrode. A interconnect structures are located in the dielectric layer and have electrical contacts with the interconnect and the gate electrode.

Abstract translation: 本发明的半导体基板上的埋入接触结构如下。 栅极绝缘体位于衬底的一部分上，栅电极位于栅极绝缘体上方。 栅极侧壁结构位于栅电极的侧壁上。 衬底中的轻掺杂结区在栅极侧壁结构之下。 掺杂结区域在衬底中，邻接轻掺杂结区域并位于栅极绝缘体的旁边。 掺杂的掩埋接触区域位于衬底中，紧邻掺杂结区域。 互连位于掺杂掩埋接触区域的第一部分上方。 掩埋接触结构还可以包括在掺杂掩埋接触区域的第二部分上的屏蔽层。 为了形成更多的连接，埋入的接触结构还可以在互连，衬底，栅极侧壁结构和栅电极之上具有介电层。 互连结构位于电介质层中并且与互连和栅电极具有电接触。

公开(公告)号：US6127698A

公开(公告)日：2000-10-03

申请号：US46343

申请日：1998-03-23

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/30 ,  H01L29/06 ,  H01L29/788

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/28273 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825

Abstract: The present invention proposes a structure of nonvolatile memory cell with a textured tunnel oxide and a high capacitive-coupling ratio. A non-tunnel oxide is formed on the semiconductor substrate. The tunnel oxides with textured surfaces are formed on the semiconductor substrate and are separated by the non-tunnel oxide. The source and drain are formed aligned to the tunnel oxides in the semiconductor substrate. The floating gate, the interpoly dielectric and the control gate, are formed in turn over the tunnel and non-tunnel oxides. Due to the textured structure of the tunnel oxide, the high-density and high-speed nonvolatile memory can be achieved.

Abstract translation: 本发明提出了具有纹理化隧道氧化物和高电容耦合比的非易失性存储单元的结构。 在半导体衬底上形成非隧道氧化物。 具有纹理表面的隧道氧化物形成在半导体衬底上，并被非隧道氧化物分离。 源极和漏极形成为与半导体衬底中的隧道氧化物对准。 浮动栅极，多晶硅电介质和控制栅极依次形成隧道和非隧道氧化物。 由于隧道氧化物的纹理结构，可以实现高密度和高速非易失性存储器。

公开(公告)号：US6117768A

公开(公告)日：2000-09-12

申请号：US99705

申请日：1998-06-19

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/768 ,  H01L23/485 ,  H01L21/4763

CPC classification number: H01L21/76864 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L2924/0002

Abstract: A doped oxide and an undoped oxide are formed on a substrate. Then, the substrate is annealed to re-flow the doped oxide layer. The doped oxide is then etched back. Next, a contact hole is created by etching. An amorphous silicon layer is formed on the surface of the doped oxide layer and along the surface of the contact hole. Next, high temperature is used to recover the etching damage and simultaneously transform or convert the amorphous silicon into a polysilicon layer. A titanium layer and a titanium nitride are respectively formed onto the polysilicon layer. Next, rapid thermal process (RTP) is introduced to form a titanium silicide beneath the titanium nitride layer. A tungsten layer is formed on the titanium nitride layer and refilled into the contact hole. The tungsten layer is then etched back to form a tungsten plug with void-free in the contact hole. A conductive layer is formed on the titanium nitride layer. The titanium silicide, titanium nitride layer and the conductive layer are patterned to define a metal line.

Abstract translation: 掺杂的氧化物和未掺杂的氧化物形成在衬底上。 然后，将衬底退火以重新流过掺杂的氧化物层。 然后将掺杂的氧化物回蚀刻。 接下来，通过蚀刻产生接触孔。 在掺杂氧化物层的表面上并且沿着接触孔的表面形成非晶硅层。 接下来，使用高温来回收蚀刻损伤并同时将非晶硅变换或转换成多晶硅层。 在多晶硅层上分别形成钛层和氮化钛。 接下来，引入快速热处理（RTP）以在氮化钛层下形成硅化钛。 在氮化钛层上形成钨层，并重新填充到接触孔中。 然后将钨层回蚀刻以在接触孔中形成无空隙的钨丝塞。 在氮化钛层上形成导电层。 将硅化钛，氮化钛层和导电层图案化以限定金属线。

公开(公告)号：US6117754A

公开(公告)日：2000-09-12

申请号：US76024

申请日：1998-05-11

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/768 ,  H01L21/8244 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/11 ,  H01L21/76895

Abstract: The present invention provides a method of forming buried contacts on a semiconductor substrate. The steps are as follows. At first, a gate insulator layer is formed over the substrate. A first silicon layer is then formed over the gate insulator layer. A buried contact opening is defined through the first silicon layer and the gate insulator layer extending down to the substrate. The substrate is then doped with a region under the buried contact opening for forming a buried contact region. A second silicon layer is formed over the substrate and the first silicon layer. A portion of the second silicon layer is then removed to define a gate region and an interconnect. Next, the substrate is doped for forming a second doping region under a region uncovered by the gate region and the interconnect. A thermal oxidation process is performed to oxidize an exposed portion of the first silicon layer and a portion of the second silicon layer at a top surface. Sidewall structures are then formed on sidewalls of the interconnect and the gate region. The substrate is doped for forming a third doping region in the second doping region under a region uncovered by the sidewall structures.

Abstract translation: 本发明提供一种在半导体衬底上形成掩埋触点的方法。 步骤如下。 首先，在衬底上形成栅极绝缘体层。 然后在栅极绝缘体层上形成第一硅层。 通过第一硅层和向下延伸到衬底的栅极绝缘体层限定埋入的接触开口。 然后将衬底掺杂在埋入触点开口下方的区域，以形成掩埋接触区域。 在衬底和第一硅层之上形成第二硅层。 然后去除第二硅层的一部分以限定栅极区和互连。 接下来，衬底被掺杂以在由栅极区域和互连件未覆盖的区域下形成第二掺杂区域。 进行热氧化处理以在顶表面氧化第一硅层的暴露部分和第二硅层的一部分。 然后在互连和栅极区域的侧壁上形成侧壁结构。 衬底被掺杂以在第二掺杂区域内在由侧壁结构未覆盖的区域下形成第三掺杂区域。

公开(公告)号：US6117731A

公开(公告)日：2000-09-12

申请号：US270908

申请日：1999-03-15

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC classification number: H01L21/28273 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/518 ,  H01L29/66825 ,  H01L21/28194 ,  H01L21/28211

Abstract: The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers are formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers are removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. The oxide is then removed, and a further oxide is re-deposited on the gate and substrate. Polysilicon side wall spacers are then formed. A further polysilicon layer is subsequently deposited over the gate. Then, the polysilicon layer is patterned to define the floating gate. A dielectric is formed at the top of the floating gate. A conductive layer is formed on the dielectric layer as the control gate.

Abstract translation: 本发明的方法包括图案化栅极结构。 然后，在栅极结构的侧壁上形成多
氧化物层。 然后，在栅极结构的侧壁上形成氮化硅侧壁间隔物。 然后，制造器件的源极/漏极结构。 接下来，去除侧壁间隔物以暴露源和漏的一部分。 然后，在栅极结构的表面，氧化物层和暴露的源极和漏极上形成未掺杂的非晶硅层。 使用干式氧化工艺将非晶硅层转变成在衬底和氧化物的界面处的纹理化隧道氧化物。 然后去除氧化物，并且另外的氧化物重新沉积在栅极和衬底上。 然后形成多晶硅侧壁间隔物。 随后在栅极上沉积另外的多晶硅层。 然后，将多晶硅层图案化以限定浮置栅极。 在浮动栅极的顶部形成电介质。 在作为控制栅极的电介质层上形成导电层。