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公开(公告)号：US07659599B2
公开(公告)日：2010-02-09
申请号：US12049258
申请日：2008-03-14
IPC分类号： H01L29/00
CPC分类号： H01L21/76243
摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.
摘要翻译： 在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。 该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。 提供了许多其他方面。
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公开(公告)号：US07659168B2
公开(公告)日：2010-02-09
申请号：US11266740
申请日：2005-11-03
IPC分类号： H01L21/336
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a first apparatus is provided. The first apparatus is an eFuse including (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是eFuse，包括（1）衬底的绝缘氧化物层上方的半导体层; （2）形成在半导体层中的二极管; 和（3）二极管上形成的硅化物层。 提供了许多其他方面。
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53.发明授权公开(公告)号：US07645645B2
公开(公告)日：2010-01-12
申请号：US11372334
申请日：2006-03-09
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.
摘要翻译： 提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分相对于熔丝结构的支撑表面驻留在不同的高度处，并且互连熔丝元件在第一端子部分和第二端子部分的不同高度之间转变。 第一端子部分和第二端子部分平行于支撑表面定向，而熔丝元件包括垂直于支撑表面定向的部分，并且包括至少一个直角弯曲部，其从第一和第二端子部分中的至少一个过渡到 保险丝元件的正交取向部分。
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54.发明授权CMOS devices adapted to prevent latchup and methods of manufacturing the same 失效适于防止闭锁的CMOS器件及其制造方法公开(公告)号：US07615828B2
公开(公告)日：2009-11-10
申请号：US11456357
申请日：2006-07-10
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/7833 , H01L21/743 , H01L21/823814 , H01L21/823878 , H01L27/0921 , H01L29/665 , H01L2027/1189
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a semiconductor device on a substrate that includes (1) a first metal-oxide-semiconductor field-effect transistor (MOSFET); (2) a second MOSFET coupled to the first MOSFET, wherein portions of the first and second MOSFETs form first and second bipolar junction transistors (BJTs) which are coupled into a loop; and (3) a conductive region that electrically couples a source diffusion region of the first or second MOSFET with a doped well region below the source diffusion region. The conductive region is adapted to prevent an induced current from forming in the loop. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是衬底上的半导体器件，其包括：（1）第一金属氧化物半导体场效应晶体管（MOSFET）; （2）耦合到所述第一MOSFET的第二MOSFET，其中所述第一和第二MOSFET的部分形成耦合到环路中的第一和第二双极结型晶体管（BJT）; 和（3）将第一或第二MOSFET的源极扩散区域与源极扩散区域下方的掺杂阱区域电耦合的导电区域。 导电区域适于防止在环路中形成感应电流。 提供了许多其他方面。
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公开(公告)号：US07477541B2
公开(公告)日：2009-01-13
申请号：US11353493
申请日：2006-02-14
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。 控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由 存储元件在第一模式下操作。 提供了许多其他方面。
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56.发明授权公开(公告)号：US07087948B2
公开(公告)日：2006-08-08
申请号：US10995444
申请日：2004-11-23
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.
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公开(公告)号：US07026202B2
公开(公告)日：2006-04-11
申请号：US10703123
申请日：2003-11-06
IPC分类号： H01L21/338
CPC分类号： H01L29/4983 , H01L21/28061 , H01L21/28114 , H01L29/42368 , H01L29/66492 , H01L29/66537 , H01L29/66553 , H01L29/66583 , H01L29/66598 , H01L29/66666
摘要： A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the center. Doping can also be different under the wings than along the center portion or beyond the gate. Regions under the wings may be doped differently than the gate conductor. With a substantially vertical implant, a region of the channel overlapped by an edge of the gate is implanted without implanting a center portion of the channel, and this region is blocked from receiving at least a portion of the received by thick portions of the gate electrode.
摘要翻译： 场效应晶体管具有具有较厚中心部分和较薄翼的逆T栅极导体。 翼可以是与中心部分不同的材料。 此外，栅极电介质可以沿着边缘比在中心更厚。 翅膀下的掺杂也可以不同于沿着中心部分或超出门。 机翼下方的区域可能与栅极导体的掺杂不同。 利用基本上垂直的注入，在不注入沟道的中心部分的情况下注入与栅极的边缘重叠的沟道的区域，并且阻止该区域接收栅电极的所接收的较厚部分的至少一部分 。
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58.发明授权公开(公告)号：US06440788B2
公开(公告)日：2002-08-27
申请号：US09895159
申请日：2001-07-02
IPC分类号： H01L2710
CPC分类号： H01L29/7302 , H01L21/84 , H01L27/1203
摘要： A multi-function semiconductor device is provided. The device includes a bipolar transistor and an FET formed in parallel. A semiconductor substrate is provided on an insulating layer. A source/emitter region and a drain region are formed in the semiconductor substrate and border first opposite sides of a body region therebetween. A gate is formed above the substrate between the source/emitter region and the drain region to form an FET having three terminals including the gate, the source/emitter region, and the drain region. A collector region is formed in the substrate abutting the drain region and extending further under the gate and the drain region. A bipolar transistor having three terminals is formed including a base region, the source/emitter, and the collector region. A shortest distance between the collector region and the source/emitter region defines a base width.
摘要翻译： 提供了多功能半导体器件。 该器件包括并联形成的双极晶体管和FET。 半导体衬底设置在绝缘层上。 源极/发射极区域和漏极区域形成在半导体衬底中并且与其间的体区域的第一相对侧边界。 在源极/发射极区域和漏极区域之间的衬底上方形成栅极，以形成具有包括栅极，源极/发射极区域和漏极区域的三个端子的FET。 集电极区域形成在与衬底邻接的衬底中，并在栅极和漏极区域之下进一步延伸。 形成具有三个端子的双极晶体管，其包括基极区域，源极/发射极和集电极区域。 集电极区域和源极/发射极区域之间的最短距离定义基极宽度。
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59.发明授权公开(公告)号：US06429477B1
公开(公告)日：2002-08-06
申请号：US09702315
申请日：2000-10-31
IPC分类号： H01L2976
CPC分类号： H01L27/10861 , H01L21/743 , H01L21/76897 , H01L27/0214 , H01L27/10888 , H01L27/1203
摘要： The preferred embodiment overcomes the difficulties found in the background art by providing a body contact and diffusion contact formed in a single shared via for silicon on insulator (SOI) technologies. By forming the body contact and diffusion contact in a single shared via, device size is minimized and performance is improved. Particularly, the formed body contact connects the SOI layer with the underlying substrate to avoid instabilities and leakage resulting from a floating SOI channel region. The formed diffusion contact connects device diffusions to above wiring to facilitate device operation. By providing the body contact and diffusion contact together in a single shared via, the preferred embodiment avoids the area penalty that would result from separate contacts. Additionally, the preferred embodiment provides a body contact that is self aligned with other devices, minimizing tolerances needed while minimizing process complexity. Additionally, the shared via body contact and diffusion contact can be selectively formed borderless to adjacent gate conductors in the device.
摘要翻译： 优选实施例通过提供在用于绝缘体上硅（SOI）技术的单个共享通孔中形成的体接触和扩散接触来克服背景技术中发现的困难。 通过在单个共享通孔中形成体接触和扩散接触，器件尺寸最小化并且性能得到改善。 特别地，形成的体接触将SOI层与底层衬底连接，以避免由浮动SOI沟道区产生的不稳定性和漏电。 形成的扩散触点将器件扩散连接到上述布线以便于器件操作。 通过在单个共享通孔中将身体接触和扩散接触提供在一起，优选的实施例避免了由单独接触引起的区域损失。 此外，优选实施例提供与其他装置自对准的身体接触，使尽可能少的过程复杂性所需的公差最小化。 此外，共享的通孔体接触和扩散接触可以选择性地形成与设备中的相邻栅极导体无边界。
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公开(公告)号：US06255694B1
公开(公告)日：2001-07-03
申请号：US09484198
申请日：2000-01-18
IPC分类号： H01L2701
CPC分类号： H01L29/7302 , H01L21/84 , H01L27/1203
摘要： A multi-function semiconductor device is provided. The device includes a bipolar transistor and an FET formed in parallel. A semiconductor substrate is provided on an insulating layer. A source/emitter region and a drain region are formed in the semiconductor substrate and border first opposite sides of a body region therebetween. A gate is formed above the substrate between the source/emitter region and the drain region to form an FET having three terminals including the gate, the source/emitter region, and the drain region. A collector region is formed in the substrate abutting the drain region and extending further under the gate and the drain region. A bipolar transistor having three terminals is formed including a base region, the source/emitter, and the collector region. A shortest distance between the collector region and the source/emitter region defines a base width.
摘要翻译： 提供了多功能半导体器件。 该器件包括并联形成的双极晶体管和FET。 半导体衬底设置在绝缘层上。 源极/发射极区域和漏极区域形成在半导体衬底中并且与其间的体区域的第一相对侧边界。 在源极/发射极区域和漏极区域之间的衬底上方形成栅极，以形成具有包括栅极，源极/发射极区域和漏极区域的三个端子的FET。 集电极区域形成在与衬底邻接的衬底中，并在栅极和漏极区域之下进一步延伸。 形成具有三个端子的双极晶体管，其包括基极区域，源极/发射极和集电极区域。 集电极区域和源极/发射极区域之间的最短距离定义基极宽度。
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