公开(公告)号：US08014197B2

公开(公告)日：2011-09-06

申请号：US12604904

申请日：2009-10-23

申请人： Nima Mokhlesi ,  Daniel C. Guterman

发明人： Nima Mokhlesi ,  Daniel C. Guterman

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3481 ,  G11C2211/5621

摘要： A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated. According to another aspect, during a program operation the current limit allowed for a cell depends upon the target state to which it is to be programmed.

摘要翻译： 提出了一种用于在非易失性集成存储器件中快速高效地编程难编程存储元件的系统和方法。 多个存储元件同时进行编程处理，其中流过存储元件的电流限于第一级。 随着这些存储元件的一部分达到规定的状态，它们被从被编程的单元组移除，并且提高了继续编程的元件上的电流限制。 这些难以编程的单元格中的当前级别可以提高到第二个，更高的限制或不受管制。 根据另一方面，在程序操作期间，允许单元的电流限制取决于要被编程的目标状态。

公开(公告)号：US07975209B2

公开(公告)日：2011-07-05

申请号：US11694950

申请日：2007-03-31

申请人： Henry Chin ,  Nima Mokhlesi

发明人： Henry Chin ,  Nima Mokhlesi

IPC分类号： H03M13/00

CPC分类号： G06F12/0246 ,  G06F2212/7209 ,  H03M13/1102

摘要： Data in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data can be performed to. The simulated annealing can introduce randomness, as noise for example, into the decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.

摘要翻译： 使用迭代概率解码对非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，将初始可靠性度量（诸如对数似然比）用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 可以执行使用基于数据中的误差水平的可调节温度参数的模拟退火。 模拟退火可以将随机性作为噪声引入到解码过程中。 此外，可以使用器件特性的知识来引导模拟退火过程，而不是引入绝对随机性。 引入一定程度的随机性增加了灵活性，允许在数据可能不可纠正的情况下可能更快的收敛时间和收敛。

公开(公告)号：US07877665B2

公开(公告)日：2011-01-25

申请号：US11618694

申请日：2006-12-29

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C29/00

CPC分类号： G06F11/1072

摘要： A data structure for a memory device is provided. The device includes an array having a plurality of rows of storage elements divided into logical units composed of a plurality of data structures. The data structure includes a data sector including user data and user attribute data. The user attribute data includes error correction coding (ECC) for the user data. The user attribute data includes information for other sectors in the logical unit. The data sector is provided in one of the plurality of rows having a higher degree of data integrity than others of said plurality of rows.

摘要翻译： 提供了一种用于存储器件的数据结构。 该装置包括具有被划分成由多个数据结构构成的逻辑单元的多行存储元件的阵列。 数据结构包括包括用户数据和用户属性数据的数据扇区。 用户属性数据包括用户数据的纠错编码（ECC）。 用户属性数据包括用于逻辑单元中其他扇区的信息。 所述数据扇区被提供在所述多个行之一中，其数据完整性高于所述多个行中的其他行。

公开(公告)号：US07859932B2

公开(公告)日：2010-12-28

申请号：US12338879

申请日：2008-12-18

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C7/00

CPC分类号： G11C16/3418 ,  G11C16/3431

摘要： Techniques are disclosed to refresh data in a non-volatile storage device often enough to combat erroneous or corrupted data bits, but not so often as to interfere with memory access or to cause excessive stress on the memory cells. One embodiment includes determining to perform a refresh of data stored in a first group of non-volatile storage elements in a device based on a condition of data in the first group, determining that a second group of non-volatile storage elements in the device should undergo a refresh procedure based on when the second group of non-volatile storage elements were last programmed relative to when the first group of non-volatile storage elements were last programmed, and performing the refresh procedure on the second group of non-volatile storage element.

摘要翻译： 公开了用于在非易失性存储设备中刷新数据的技术，其足以抵抗错误或损坏的数据位，但不会频繁地干扰存储器访问或者对存储器单元造成过度的应力。 一个实施例包括确定基于第一组中的数据的条件来执行存储在设备中的第一组非易失性存储元件中的数据的刷新，确定设备中的第二组非易失性存储元件应该 基于当第二组非易失性存储元件被最后编程为相对于第一组非易失性存储元件最后被编程的时间的时间来执行刷新过程，并且对第二组非易失性存储元件执行刷新过程 。

公开(公告)号：US07808832B2

公开(公告)日：2010-10-05

申请号：US12371479

申请日：2009-02-13

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C16/06

CPC分类号： G11C16/26

摘要： In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level.

摘要翻译： 在感测多状态非易失性存储器中的一组单元时，需要相对于不同分界阈值电平的多个感测周期来解决所有可能的多个存储器状态。 每个感测周期都有一个感测通道。 它还可以包括预感测通过或子周期，以识别其阈值电压低于当前正在被感测的分界阈值水平的单元。 这些是更高的电流单元，可以关闭以实现省电和减少源偏置误差。 通过将它们的相关位线锁定到地来关闭电池。 然后，重复感应通过将产生更准确的结果。 提供电路和方法来选择性地启用或禁用位线锁定和预感测，以便提高性能，同时确保感测操作不消耗超过最大电流电平。

公开(公告)号：US07745285B2

公开(公告)日：2010-06-29

申请号：US11693765

申请日：2007-03-30

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from a first layer and even numbered floating gates from a second layer.

摘要翻译： 形成一组非易失性存储单元，其中控制栅极在浮置栅极，控制栅极和由隧道介电层分开的浮动栅极之间延伸。 控制门和浮动门之间的电子隧穿用于编程。 用于形成存储器阵列的过程从第一层形成奇数浮动栅极，并且从第二层形成偶数编号的浮动栅极。

公开(公告)号：US07745265B2

公开(公告)日：2010-06-29

申请号：US11691885

申请日：2007-03-27

申请人： Nima Mokhlesi ,  Roy Scheuerlein

发明人： Nima Mokhlesi ,  Roy Scheuerlein

IPC分类号： H01L21/82

CPC分类号： H01L27/11568 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11582

摘要： A method of making a monolithic, three dimensional NAND string, includes forming a select transistor, forming a first memory cell over a second memory cell, forming a first word line for the first memory cell, forming a second word line for the second memory cell, forming a bit line, forming a source line, and forming a select gate line for the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.

摘要翻译： 制造单片三维NAND串的方法包括形成选择晶体管，在第二存储单元上形成第一存储单元，形成第一存储单元的第一字线，形成用于第二存储单元的第二字线 形成位线，形成源极线，并形成用于选择晶体管的选择栅极线。 第一和第二字线不平行于位线，并且第一和第二字线平行于源极线和选择栅极线中的至少一个延伸。

公开(公告)号：US07696035B2

公开(公告)日：2010-04-13

申请号：US11558986

申请日：2006-11-13

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/11521 ,  H01L27/11524

摘要： A method for fabricating a non-volatile memory having boost structures. Boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or verify level. The boost structures assists in programming so that the programming and pass voltage on a word line can be reduced, thereby reducing side effects such as program disturb. During verifying, all storage elements on a word line can be verified concurrently. The boost structure can also assist during reading. In one approach, the NAND string has dual source-side select gates between which the boost structure contacts the substrate at a source/drain region, and a boost voltage is provided to the boost structure via a source-side of the NAND string.

摘要翻译： 一种用于制造具有升压结构的非易失性存储器的方法。 提供单独NAND串的Boost结构，并且可以单独控制以协助编程，验证和读取过程。 升压结构可以通常被提升和单独放电，部分地基于目标编程状态或验证电平。 升压结构有助于编程，从而可以减少字线上的编程和通过电压，从而减少诸如程序干扰的副作用。 在验证期间，可以同时验证字线上的所有存储元素。 升压结构也可以在阅读过程中有所帮助。 在一种方法中，NAND串具有双源极选择栅极，在该源极/漏极区域之间升压结构与衬底接触，并且经由NAND串的源极侧将升压电压提供给升压结构。

公开(公告)号：US20100014349A1

公开(公告)日：2010-01-21

申请号：US12339005

申请日：2008-12-18

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C11/56 ,  G11C16/10 ,  G11C16/04

CPC分类号： G11C16/349 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641

摘要： A non-volatile storage system stores data by programming the data as binary data into blocks that have not yet been programmed with multi-state data and have not yet been programmed with binary data X times. The system transfers data from multiple blocks (source blocks) of binary data to one block (target block) of multi-state data using a multi-state programming process, where the target block has been previously programmed with binary data X times (or less than X times).

摘要翻译： 非易失性存储系统通过将数据作为二进制数据编程为尚未被编程为多状态数据并且尚未被二进制数据X编程的块来存储数据。 该系统使用多状态编程过程将数据从多个二进制数据的块（源块）传送到多状态数据的一个块（目标块），其中目标块已经被预先用二进制数据X次（或更少） 比X倍）。

公开(公告)号：US07616500B2

公开(公告)日：2009-11-10

申请号：US11694989

申请日：2007-03-31

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C11/34

CPC分类号： G11C8/10 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A set of non-volatile storage elements are erased to an erased threshold voltage distribution. A multi-pass programming process is performed that programs the set of non-volatile storage elements from the erased threshold voltage distribution to a set valid data threshold voltage distributions. Each programming pass has one or more starting threshold voltage distributions and programs non-volatile storage elements to at least two ending threshold voltage distributions.

摘要翻译： 一组非易失性存储元件被擦除为擦除的阈值电压分布。 执行多遍编程处理，其将该非易失性存储元件组从擦除的阈值电压分布编程到设定的有效数据阈值电压分布。 每个编程遍具有一个或多个起始阈值电压分布，并将非易失性存储元件编程为至少两个结束阈值电压分布。