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公开(公告)号：US08284621B2
公开(公告)日：2012-10-09
申请号：US12705674
申请日：2010-02-15
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C8/18
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。
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公开(公告)号：US08257092B2
公开(公告)日：2012-09-04
申请号：US12946328
申请日：2010-11-15
申请人： Sungjun Chun , Daniel M. Dreps , Dierk Kaller , Rohan U. Mandrekar , Lei Shan
发明人： Sungjun Chun , Daniel M. Dreps , Dierk Kaller , Rohan U. Mandrekar , Lei Shan
IPC分类号： H01R12/00
摘要： A memory module configured to connect to a slot of a data processing system. A set of tabs is connected to the module and configured to electrically connect the module to the slot and to electrically connect the module to a clock of the data processing system. The set of tabs includes a first tab, a second tab, a third tab, and a fourth tab. The first tab and the second tab are opposite the third tab and the fourth tab. The first tab comprises a positive type tab, the second tab comprises a negative type tab, the third tab comprises a positive type tab, and the fourth tab comprises a negative type tab. The first and third tabs are configured to provide a first electrical connection to the clock. The second and fourth tabs are configured to provide a second electrical connection to the clock. Together, the first, second, third, and fourth tabs comprise two dual tabs.
摘要翻译： 配置为连接到数据处理系统的时隙的存储器模块。 一组标签连接到模块并且被配置为将模块电连接到插槽并且将模块电连接到数据处理系统的时钟。 该组标签包括第一标签，第二标签，第三标签和第四标签。 第一个选项卡和第二个选项卡与第三个选项卡和第四个选项卡相对。 第一标签包括一个正型标签，该第二标签包括一个负型标签，该第三标签包括一个正型标签，该第四标签包括一个负型标签。 第一和第三选项卡被配置为提供到时钟的第一电连接。 第二和第四选项卡被配置为提供与时钟的第二电连接。 一起，第一，第二，第三和第四标签包括两个双标签。
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53.发明授权公开(公告)号：US07948817B2
公开(公告)日：2011-05-24
申请号：US12394804
申请日：2009-02-27
申请人： Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Kenneth L. Wright
发明人： Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Kenneth L. Wright
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G06F13/1689 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/222 , G11C8/12 , Y02D10/14
摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.
摘要翻译： 一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。 可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。 无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及 输出延迟时钟。 输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。
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公开(公告)号：US07932705B2
公开(公告)日：2011-04-26
申请号：US12178678
申请日：2008-07-24
申请人： Seongwon Kim , Daniel M. Dreps
发明人： Seongwon Kim , Daniel M. Dreps
CPC分类号： G05F1/561
摘要： A variable input voltage regulator includes a first circuit configured to convert a first voltage from a first voltage source to a first current, and a second circuit electrically coupled to the first circuit and configured to mirror the first current to a voltage output node. The variable input voltage regulator further includes a third circuit electrically coupled to the voltage output node of the second circuit and configured to supply additional current to the voltage output node from a second voltage of a second voltage source in response to a control input.
摘要翻译： 可变输入电压调节器包括被配置为将第一电压从第一电压源转换为第一电流的第一电路，以及电耦合到第一电路并被配置为将第一电流镜像到电压输出节点的第二电路。 可变输入电压调节器还包括电耦合到第二电路的电压输出节点并被配置为响应于控制输入从第二电压源的第二电压向电压输出节点提供附加电流的第三电路。
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公开(公告)号：US07890676B2
公开(公告)日：2011-02-15
申请号：US12185533
申请日：2008-08-04
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller; an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller.
摘要翻译： 公开了包括存储器控制器的存储器系统; 出站链路，连接到出站链路的存储器控制器，出站链路包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器设备的多个导电路径; 以及第一存储器层中的至少两个存储器缓冲器件，所述第一存储器层中的每个存储器缓冲器件连接到所述出站链路以从所述存储器控制器接收存储器信号。
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56.发明授权Configurable pre-emphasis driver with selective constant and adjustable output impedance modes 失效可配置预加重驱动器，具有选择性恒定和可调输出阻抗模式公开(公告)号：US07888968B2
公开(公告)日：2011-02-15
申请号：US12354007
申请日：2009-01-15
IPC分类号： H03K19/094 , H03K17/16
CPC分类号： H04B3/145
摘要： Embodiments of the invention are directed to a single driver that can be used to transmit data with configurable levels of pre-emphasis, and can have either a constant or adjustable driver output impendence, selectively. One embodiment, directed to a driver apparatus, is associated with a digital communication channel for transmitting data signals, wherein at least one of the signals includes a higher frequency component. The apparatus comprises a first sub-driver that has a constant output impedance, and is selectively configurable to implement two or more different levels of pre-emphasis. The apparatus further comprises one or more second sub-drivers. A set of connector elements are provided for connecting the first sub-driver and each of the second sub-drivers in parallel relationship with one another, so that the first sub-driver and each of the second sub-drivers all have inputs that respectively receive a specified driver apparatus input signal, and all have outputs that are connected together to selectively provide a specified driver apparatus output impedance. The apparatus further includes a device that is connected to selectively disable and enable each of the second sub-drivers.
摘要翻译： 本发明的实施例涉及可用于传输具有可配置水平的预加重的数据的单个驱动器，并且可以选择性地具有恒定的或可调节的驱动器输出阻抗。 针对驱动器装置的一个实施例与用于传输数据信号的数字通信信道相关联，其中信号中的至少一个包括较高频率分量。 该装置包括具有恒定输出阻抗的第一子驱动器，并且可选择性地配置为实现两个或多个不同级别的预加重。 该装置还包括一个或多个第二子驱动器。 提供了一组连接器元件，用于将第一子驱动器和每个第二子驱动器彼此并联连接，使得第一子驱动器和每个第二子驱动器都具有分别接收的输入 指定的驱动器装置输入信号，并且都具有连接在一起的输出，以选择性地提供指定的驱动器装置输出阻抗。 该装置还包括被连接以选择性地禁用并启用每个第二子驱动器的装置。
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公开(公告)号：US07710144B2
公开(公告)日：2010-05-04
申请号：US12165804
申请日：2008-07-01
CPC分类号： G06F13/4072 , G06F13/4086
摘要： A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an external reference resistor, and driver circuitry including multiple positive drive circuits and multiple negative drive circuits coupled to a driver output in a memory system. The memory interface device further includes impedance control logic to adjust the output impedance of the calibration cell and selectively enable the positive and negative drive circuits as a function of a drive voltage and a target impedance.
摘要翻译： 提供了一种用于控制存储器系统中的可变阻抗和电压的存储器接口设备，系统，方法和设计结构。 存储器接口装置包括可配置为相对于外部参考电阻器调整输出阻抗的校准单元，以及包括耦合到存储器系统中的驱动器输出的多个正驱动电路和多个负驱动电路的驱动器电路。 存储器接口装置还包括阻抗控制逻辑，用于调整校准单元的输出阻抗，并且选择性地使正和负驱动电路作为驱动电压和目标阻抗的函数。
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58.发明授权Signal history controlled slew-rate transmission method and bus interface transmitter 失效信号历史控制压摆率传输方式和总线接口发射机公开(公告)号：US07696787B2
公开(公告)日：2010-04-13
申请号：US11962093
申请日：2007-12-21
IPC分类号： H03K19/0175 , H03B5/22
CPC分类号： H04L25/0286 , H04L25/0272
摘要： A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.
摘要翻译： 信号历史控制的转换速率传输方法和总线接口发射机提供了一种具有低复杂度的改进的信道均衡机制。 可变转换速率前馈预加重电路根据发送信号的历史改变所施加的预加重的转换速率。 预加重电路可以由提供发射机的输出并具有不同电流值的一对电流源来实现。 控制电流源，使得在信号值变化时，提供高压摆率，并且当两个连续信号周期的信号值不变时，转换速率降低。 可以使用具有受控幅度的电流源来提供随时间变化的压摆率，并且持续地减小，直到发生另一个传输值变化。
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公开(公告)号：US20100019744A1
公开(公告)日：2010-01-28
申请号：US12178678
申请日：2008-07-24
申请人： Seongwon Kim , Daniel M. Dreps
发明人： Seongwon Kim , Daniel M. Dreps
IPC分类号： G05F1/10
CPC分类号： G05F1/561
摘要： A variable input voltage regulator includes a first circuit configured to convert a first voltage from a first voltage source to a first current, and a second circuit electrically coupled to the first circuit and configured to mirror the first current to a voltage output node. The variable input voltage regulator further includes a third circuit electrically coupled to the voltage output node of the second circuit and configured to supply additional current to the voltage output node from a second voltage of a second voltage source in response to a control input.
摘要翻译： 可变输入电压调节器包括被配置为将第一电压从第一电压源转换为第一电流的第一电路，以及电耦合到第一电路并被配置为将第一电流镜像到电压输出节点的第二电路。 可变输入电压调节器还包括电耦合到第二电路的电压输出节点并被配置为响应于控制输入从第二电压源的第二电压向电压输出节点提供附加电流的第三电路。
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公开(公告)号：US20100001758A1
公开(公告)日：2010-01-07
申请号：US12165804
申请日：2008-07-01
IPC分类号： H03K17/16 , G11C8/00 , H03K19/0175
CPC分类号： G06F13/4072 , G06F13/4086
摘要： A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an external reference resistor, and driver circuitry including multiple positive drive circuits and multiple negative drive circuits coupled to a driver output in a memory system. The memory interface device further includes impedance control logic to adjust the output impedance of the calibration cell and selectively enable the positive and negative drive circuits as a function of a drive voltage and a target impedance.
摘要翻译： 提供了一种用于控制存储器系统中的可变阻抗和电压的存储器接口设备，系统，方法和设计结构。 存储器接口装置包括可配置为相对于外部参考电阻器调整输出阻抗的校准单元，以及包括耦合到存储器系统中的驱动器输出的多个正驱动电路和多个负驱动电路的驱动器电路。 存储器接口装置还包括阻抗控制逻辑，用于调整校准单元的输出阻抗，并且选择性地使正和负驱动电路作为驱动电压和目标阻抗的函数。
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