公开(公告)号：US08546869B2

公开(公告)日：2013-10-01

申请号：US13600829

申请日：2012-08-31

申请人： Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

发明人： Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

IPC分类号： H01L21/8239

CPC分类号： G11C16/28 ,  G11C16/14 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/7889 ,  H01L29/7926

摘要： Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.

摘要翻译： 形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。 这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串 系列。

公开(公告)号：US20120327715A1

公开(公告)日：2012-12-27

申请号：US13600829

申请日：2012-08-31

申请人： Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

发明人： Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

IPC分类号： G11C16/06

CPC分类号： G11C16/28 ,  G11C16/14 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/7889 ,  H01L29/7926

摘要： Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.

摘要翻译： 形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。 这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串 系列。

公开(公告)号：US20130171806A1

公开(公告)日：2013-07-04

申请号：US13779334

申请日：2013-02-27

申请人： Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

发明人： Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

IPC分类号： H01L21/02

CPC分类号： H01L21/02365 ,  H01L21/02697 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.

摘要翻译： 提供一种三维半导体存储器件。 三维半导体存储器件包括具有包括一对子单元区域的单元阵列区域和插入该一对子单元区域之间的带状区域的基板。 多个子栅极依次层叠在每个子单元区域中的衬底上，并且互连电连接到延伸到捆扎区域中的堆叠子栅极的延伸部分。 每个互连电连接到分别设置在一对子单元区域中并且位于同一电平的子栅极的延伸部分。

公开(公告)号：US08278170B2

公开(公告)日：2012-10-02

申请号：US13165576

申请日：2011-06-21

申请人： Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

发明人： Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

IPC分类号： H01L21/336

CPC分类号： G11C16/28 ,  G11C16/14 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/7889 ,  H01L29/7926

摘要： Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.

摘要翻译： 形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。 这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串 系列。

公开(公告)号：US20100254191A1

公开(公告)日：2010-10-07

申请号：US12752485

申请日：2010-04-01

申请人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

发明人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

IPC分类号： G11C16/02 ,  H01L21/3205

CPC分类号： H01L27/0207 ,  G11C7/18 ,  H01L23/535 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

摘要翻译： 半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 以及多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上方延伸的第二部分，其中多个 字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

公开(公告)号：US08559224B2

公开(公告)日：2013-10-15

申请号：US13028918

申请日：2011-02-16

申请人： Jinman Han ,  Sunil Shim ,  Hansoo Kim ,  Jaehoon Jang ,  Byoungkeun Son

发明人： Jinman Han ,  Sunil Shim ,  Hansoo Kim ,  Jaehoon Jang ,  Byoungkeun Son

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and selectively refreshing each sub block of the selected memory block in response to the reading of the selected sub block, wherein each sub block of the selected memory block is separately erased.

摘要翻译： 提供了一种操作包括基板的非易失性存储器件的方法和具有沿着垂直于衬底的方向堆叠的多个存储单元的存储器块。 该方法包括：响应于所选择的子块的读取，从所选择的存储器块的子块中读取选定的子块的数据并选择刷新所选存储块的每个子块，其中所选存储块的每个子块 被单独擦除。

公开(公告)号：US20110317489A1

公开(公告)日：2011-12-29

申请号：US13093320

申请日：2011-04-25

申请人： Kihyun Kim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Chulmin Park

发明人： Kihyun Kim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Chulmin Park

IPC分类号： G11C16/26

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11582

摘要： Reading methods of nonvolatile memory devices including a substrate and a plurality of memory cells which are stacked in a direction intersecting the substrate. The reading methods apply a bit line voltage to a plurality of bit lines and apply a first string selection line voltage to at least one selected string selection line. The reading methods apply a second string selection line voltage to at least one unselected string selection line and apply a read voltage to a plurality of word lines. The reading methods apply a first ground selection line voltage to at least one selected ground selection line and apply a second ground selection line voltage to at least one unselected ground selection line.

摘要翻译： 非易失性存储器件的读取方法包括在与衬底交叉的方向上堆叠的衬底和多个存储单元。 读取方法将位线电压施加到多个位线，并将第一串选择线电压施加到至少一个所选择的串选择线。 读取方法将第二串选择线电压施加到至少一个未选择的串选择线，并将读电压施加到多个字线。 读取方法将第一接地选择线电压施加到至少一个所选择的接地选择线，并将第二接地选择线电压施加到至少一个未选择的接地选择线。

公开(公告)号：US20110199825A1

公开(公告)日：2011-08-18

申请号：US13028918

申请日：2011-02-16

申请人： Jinman Han ,  Sunil Shim ,  Hansoo Kim ,  Jaehoon Jang ,  Byoungkeun Son

发明人： Jinman Han ,  Sunil Shim ,  Hansoo Kim ,  Jaehoon Jang ,  Byoungkeun Son

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and selectively refreshing each sub block of the selected memory block in response to the reading of the selected sub block, wherein each sub block of the selected memory block is separately erased.

摘要翻译： 提供了一种操作包括基板的非易失性存储器件的方法和具有沿着垂直于衬底的方向堆叠的多个存储单元的存储器块。 该方法包括：响应于所选择的子块的读取，从所选择的存储器块的子块中读取选定的子块的数据并选择刷新所选存储块的每个子块，其中所选存储块的每个子块 被单独擦除。

公开(公告)号：US20140016408A1

公开(公告)日：2014-01-16

申请号：US14024844

申请日：2013-09-12

申请人： Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

发明人： Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

IPC分类号： G11C16/28

CPC分类号： G11C16/28 ,  G11C16/14 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/7889 ,  H01L29/7926

摘要： Nonvolatile memory devices according to embodiments of the invention include highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.

摘要翻译： 根据本发明的实施例的非易失性存储器件包括高度集成的非易失性存储器单元的垂直堆叠。 这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串 系列。

公开(公告)号：US20120003800A1

公开(公告)日：2012-01-05

申请号：US13165576

申请日：2011-06-21

申请人： Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

发明人： Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

IPC分类号： H01L21/8239

CPC分类号： G11C16/28 ,  G11C16/14 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/7889 ,  H01L29/7926

摘要： Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.

摘要翻译： 形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。 这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串 系列。