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120 条记录 (耗时 0.03 秒)

    UNDISCOVERABLE PHYSICAL CHIP IDENTIFICATION
    52.
    发明申请
    UNDISCOVERABLE PHYSICAL CHIP IDENTIFICATION 有权
    不合格的物理芯片识别

    公开(公告)号：US20140033330A1

    公开(公告)日：2014-01-30

    申请号：US13561185

    申请日：2012-07-30

    申请人： Daniel Jacob Fainstein ,  Chandrasekharan Kothandaraman

    发明人： Daniel Jacob Fainstein ,  Chandrasekharan Kothandaraman

    IPC分类号： H03K5/24 ,  G06F21/00

    CPC分类号： G06F21/73 ,  G06F7/588 ,  G06F21/00 ,  G06F21/30 ,  G06F2221/2129 ,  H02H3/24 ,  H04L9/3278

    摘要： Methods and circuits for undiscoverable physical chip identification are disclosed. Embodiments of the present invention provide an intrinsic bit element that comprises two transistors. The two transistors form a pair in which one transistor has a wide variability in threshold voltage and the other transistor has a narrow variability in threshold voltage. The wide variability is achieved by making a transistor with a smaller width and length than the other transistor in the pair. The variation of the threshold voltage of the wide variability transistor means that in the case of copies of intrinsic bit elements being made, some of the “copied” wide variability transistors will have significantly different threshold voltages, causing some of the intrinsic bit elements of a copied chip to read differently than in the original chip from which they were copied.

    摘要翻译： 公开了用于不可发现的物理芯片识别的方法和电路。 本发明的实施例提供了包括两个晶体管的本征位元件。 两个晶体管形成一对，其中一个晶体管具有很大的阈值电压变化，另一个晶体管的阈值电压变化很小。 通过制造具有比该对中的另一个晶体管更小的宽度和长度的晶体管来实现广泛的变化。 宽变化率晶体管的阈值电压的变化意味着在内部位元素复制的情况下，一些“复制的”宽变化性晶体管将具有明显不同的阈值电压，导致一些固有位元素 复制芯片的读取方式与原始芯片的复制方式不同。

    Electrically programmable fuse using anisometric contacts and fabrication method
    53.
    发明授权
    Electrically programmable fuse using anisometric contacts and fabrication method 有权
    电子可编程保险丝采用不规则接触和制造方法

    公开(公告)号：US08629049B2

    公开(公告)日：2014-01-14

    申请号：US13420724

    申请日：2012-03-15

    申请人： Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

    发明人： Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

    IPC分类号： H01L21/44

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

    摘要翻译： 制造电可编程熔丝法的制造方法包括在衬底上沉积多晶硅层，图案化阳极接触区域，阴极接触区域和将阴极接触区域与阳极接触区域导电连接的熔断体，其可通过应用 编程电流，在多晶硅层上沉积硅化物层，以及在预定构型中分别在阴极接触区域和阳极接触区域的硅化物层上形成多个不规则接触。

    Programmable high-k/metal gate memory device
    54.
    发明授权
    Programmable high-k/metal gate memory device 有权
    可编程高k /金属栅极存储器件

    公开(公告)号：US08525263B2

    公开(公告)日：2013-09-03

    申请号：US12355954

    申请日：2009-01-19

    申请人： Roger A. Booth ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

    发明人： Roger A. Booth ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

    IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/78 ,  H01L21/28282 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

    摘要： A method of fabricating a memory device is provided that may begin with forming a layered gate stack overlying a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode overlying a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

    摘要翻译： 提供了一种制造存储器件的方法，其可以开始形成覆盖在半导体衬底上的层叠栅极堆叠并且图案化停止在层状栅极堆叠的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和 半导体衬底上的第二金属栅电极。 在下一个处理顺序中，在第一金属栅电极上形成至少一个间隔物，该第一金属栅电极覆盖高k栅极电介质层的一部分，其中暴露高k栅极电介质的剩余部分。 蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质 到第二金属栅电极的侧壁。

    SECURE ANTI-FUSE WITH LOW VOLTAGE PROGRAMMING THROUGH LOCALIZED DIFFUSION HEATING
    55.
    发明申请
    SECURE ANTI-FUSE WITH LOW VOLTAGE PROGRAMMING THROUGH LOCALIZED DIFFUSION HEATING 失效
    通过局部扩散加热实现低电压编程的安全保险丝

    公开(公告)号：US20130063202A1

    公开(公告)日：2013-03-14

    申请号：US13612938

    申请日：2012-09-13

    申请人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

    发明人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

    IPC分类号： H01L23/544 ,  H01H37/76

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.

    摘要翻译： 反熔丝具有一个导电类型的第一和第二半导体区域和它们之间具有相反导电类型的第三半导体区域。 接触第一区域的导电区域在横向于栅极的长尺寸方向的第二方向上具有长尺寸。 反熔丝阳极在第二方向上与第一区域间隔开，并且触点与第二区域连接。 在阳极和接触之间施加编程电压，栅极偏压足以完全导通反熔丝的场效应晶体管操作加热第一区域以向外驱动掺杂剂，导致第一区域的边缘更接近于 并且将第一和第二区域之间的电阻降低一个或多个数量级。

    RADIO FREQUENCY-ENABLED ELECTROMIGRATION FUSE
    57.
    发明申请
    RADIO FREQUENCY-ENABLED ELECTROMIGRATION FUSE 有权
    无线电频率电磁保险丝

    公开(公告)号：US20110187407A1

    公开(公告)日：2011-08-04

    申请号：US12696104

    申请日：2010-01-29

    申请人： Subramanian S. Iyer ,  Chandrasekharan Kothandaraman ,  Gerard M. Salem

    发明人： Subramanian S. Iyer ,  Chandrasekharan Kothandaraman ,  Gerard M. Salem

    IPC分类号： H03K19/173 ,  G01R31/02

    CPC分类号： G01R31/02 ,  H03K19/173

    摘要： Embodiments of the invention provides a method, device, and system for programming an electromigration fuse (eFuse) using a radio frequency (RF) signal. A first aspect of the invention provides a method of testing circuitry on a semiconductor chip, the method comprising: receiving a radio frequency (RF) signal using at least one antenna on the semiconductor chip; powering circuitry on the semiconductor chip using the RF signal; activating a built-in self test (BIST) engine within the circuitry; determining whether a fault exists within the circuitry using the BIST; and programming an electromigration fuse (eFuse) to alter the circuitry in response to a fault being determined to exist.

    摘要翻译： 本发明的实施例提供了一种使用射频（RF）信号编程电迁移保险丝（eFuse）的方法，装置和系统。 本发明的第一方面提供了一种在半导体芯片上测试电路的方法，该方法包括：使用半导体芯片上的至少一个天线接收射频（RF）信号; 使用RF信号对半导体芯片供电; 激活电路内的内置自检（BIST）引擎; 确定使用BIST的电路内是否存在故障; 以及编程电迁移保险丝（eFuse）以响应于确定存在的故障来改变电路。

    NON-VOLATILE MEMORY DEVICE USING HOT-CARRIER INJECTION
    58.
    发明申请
    NON-VOLATILE MEMORY DEVICE USING HOT-CARRIER INJECTION 有权
    使用热载体注射的非易失性存储器件

    公开(公告)号：US20100193854A1

    公开(公告)日：2010-08-05

    申请号：US12692923

    申请日：2010-01-25

    申请人： Roger Allen Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

    发明人： Roger Allen Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

    IPC分类号： H01L29/76 ,  H01L21/335

    CPC分类号： H01L29/7923 ,  H01L29/66833

    摘要： Each of a hot-carrier non-volatile memory device and a method for fabricating the hot carrier non-volatile memory device is predicated upon a semiconductor structure and related method that includes a metal oxide semiconductor field effect transistor structure. The semiconductor structure and related method include at least one of: (1) a spacer that comprises a dielectric material having a dielectric constant greater than 7 (for enhanced hot carrier derived charge capture and retention); and (2) a drain region that comprises a semiconductor material that has a narrower bandgap than a bandgap of a semiconductor material from which is comprised a channel region (for enhanced impact ionization and charged carrier generation).

    摘要翻译： 热载体非易失性存储器件和用于制造热载体非易失性存储器件的方法中的每一种都取决于包括金属氧化物半导体场效应晶体管结构的半导体结构和相关方法。 半导体结构和相关方法包括以下中的至少一个：（1）包括介电常数大于7的介电材料的间隔物（用于增强热载体导电的电荷捕获和保留）; 和（2）包括半导体材料的漏极区，该半导体材料具有比半导体材料的带隙窄的带隙，其包括沟道区（用于增强的冲击电离和带电载流子的生成）。

    PROGRAMMABLE ELECTRONIC FUSE
    59.
    发明申请
    PROGRAMMABLE ELECTRONIC FUSE 审中-公开
    可编程电子保险丝

    公开(公告)号：US20090179302A1

    公开(公告)日：2009-07-16

    申请号：US12355056

    申请日：2009-01-16

    申请人： Chandrasekharan Kothandaraman ,  Subramanian Iyer

    发明人： Chandrasekharan Kothandaraman ,  Subramanian Iyer

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A programmable device (eFuse), includes: a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having a first end (12a), a second end (12b), a fuse link (11) between the ends, and an upper surface S. The semiconductor material includes a dopant having a concentration of at least 10*17/cc. The first end (12a) is wider than the second end (12b), and a metallic material is disposed on the upper surface. The metallic material is physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and through the metallic material.

    摘要翻译： 一种可编程器件（eF​​use），包括：衬底（10）; 绝缘体（13）; 在绝缘体上的细长半导体材料（12），所述细长半导体材料具有第一端（12a），第二端（12b），端部之间的熔断体（11）和上表面S.半导体材料包括 浓度至少为10 * 17 / cc的掺杂剂。 第一端（12a）比第二端（12b）宽，并且金属材料设置在上表面上。 响应于可流过半导体材料和通过金属材料的电流I，金属材料可沿着上表面物理迁移。