公开(公告)号：US06468853B1

公开(公告)日：2002-10-22

申请号：US09641389

申请日：2000-08-18

申请人： Palanivel Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Chivkula Subrahmanyam ,  Narayanan Balasubramanian

发明人： Palanivel Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Chivkula Subrahmanyam ,  Narayanan Balasubramanian

IPC分类号： H01L218238

CPC分类号： H01L21/76235

摘要： A structure and a process for manufacturing semiconductor devices with improved oxide coverage on the corners of a shallow trench isolation structure is described. The STI trench is etched using a pad oxide and silicon nitride layers as patterning elements. After trench etch, a thin conformal layer of either amorphous, epitaxial or polysilicon is deposited over the silicon nitride and within the trench and annealed. Where the silicon has been deposited on the silicon bottom and sides of the open trench, the annealing effectively forms a single crystal or epitaxial silicon. Next a silicon oxide liner is grown over the conformal silicon layer. The trench is then filled with silicon oxide, the structure is planarized by either chemical mechanical polishing or etching, and the nitride and pad oxide is removed This leaves a polysilicon film on the vertical edges of the filler oxide which extends slightly above the surface of the silicon substrate. A thermal oxidation step is performed converting the poly film into silicon oxide which slightly extends the STI field oxide into the active device region eliminating any reduced oxide coverage or oxide recesses in the corner regions.

摘要翻译： 描述了在浅沟槽隔离结构的角上制造具有改善的氧化物覆盖的半导体器件的结构和工艺。 使用衬垫氧化物和氮化硅层作为图案化元件来蚀刻STI沟槽。 在沟槽蚀刻之后，非晶，外延或多晶硅的薄的共形层沉积在氮化硅上并在沟槽内并退火。 当硅沉积在开口沟槽的硅底部和侧面上时，退火有效地形成单晶或外延硅。 接下来，在保形硅层上生长氧化硅衬垫。 然后用氧化硅填充沟槽，通过化学机械抛光或蚀刻对该结构进行平面化，并且去除氮化物和衬垫氧化物。在填充氧化物的垂直边缘上留下多晶硅膜，其在 硅衬底。 执行热氧化步骤，将多晶硅膜转化为将STI场氧化物稍微延伸到有源器件区域中的氧化硅，消除角区域中任何减少的氧化物覆盖或氧化物凹陷。

公开(公告)号：US06387765B2

公开(公告)日：2002-05-14

申请号：US09946982

申请日：2001-09-06

申请人： Vijai Kumar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

发明人： Vijai Kumar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/41 ,  H01L29/42376 ,  H01L29/4941

摘要： A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; therein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer; whereby the metal gate layer has a greater width than the gate structure.

摘要翻译： 一种用于形成不具有聚环绕效应的延伸金属栅极的方法。 提供其上具有栅极结构的半导体结构。 栅极结构包括依次堆叠的栅极介电层，栅极硅层，掺杂氧化硅层和一次性栅极层。 隔板形成在栅极结构的侧壁上。 在半导体结构和栅极结构之上形成电介质间隙填充层，并在一次性栅极层上停止平坦化。 在一次性栅极层上形成第一氮化硅层，并且在第一氮化硅层上形成电介质层。 图案化电介质层以在栅极结构上形成沟槽; 其中沟槽的宽度大于栅极结构的宽度。 使用一个或多个选择性蚀刻工艺去除沟槽底部中的第一氮化硅层和一次性栅极层。 使用掺杂的氧化硅对未掺杂的氧化硅具有高选择性的蚀刻来去除掺杂的氧化硅层。 在栅极硅层上形成阻挡层，在阻挡层上形成金属栅极层; 由此金属栅极层具有比栅极结构更大的宽度。

公开(公告)号：US06337262B1

公开(公告)日：2002-01-08

申请号：US09519611

申请日：2000-03-06

申请人： Yelehanka Ramachandramurthy Pradeep ,  Chivukula Subrahmanyam ,  Vijai Kumar Chhagan ,  Henry Gerung

发明人： Yelehanka Ramachandramurthy Pradeep ,  Chivukula Subrahmanyam ,  Vijai Kumar Chhagan ,  Henry Gerung

IPC分类号： H01L2128

CPC分类号： H01L29/66583 ,  H01L21/28114 ,  H01L29/66553

摘要： A new method is provided for the integration of the of T-top gate process. Active regions are defined and bounded by STI's on the surface of a substrate. The pad oxide is removed from the substrate and replaced by a layer of SAC oxide. A thin layer of nitride is deposited that covers the surface of the created layer of SAC oxide and the surface of the STI regions. A layer of TEOS is deposited and etched defining the regions where the gate electrodes need to be formed. Gate spacers are next formed on the sidewalls of the openings that have been created in the layer of TEOS. The required implants (such as channel implant and threshold implant) are performed, the gate structure is then grown in the openings that have been created in the layer of TEOS. After the gate structure has been completed, the surface of the created structure is polished and the remaining layer of TEOS is removed. Source and drain regions implants can now be performed, LDD regions are implanted using a tilted implant. This tilted implant penetrates underneath the body of the created gate structures thereby creating the LDD regions. The removal of the layer of TEOS leaves in place the gate structures, one such structure is located in the active region of the surface of the substrate, two additional structures that have been created on the surface of the STI regions.

摘要翻译： 提供了一种用于集成T-top门过程的新方法。 有源区域由衬底表面上的STI限定和界定。 衬垫氧化物从衬底上去除并被一层SAC氧化物代替。 沉积薄层的氮化物，其覆盖所形成的SAC氧化物层的表面和STI区域的表面。 沉积和蚀刻一层TEOS，限定需要形成栅电极的区域。 接下来，在已经在TEOS层中形成的开口的侧壁上形成栅极间隔物。 执行所需的植入物（例如通道植入和阈值植入），然后在已经在TEOS层中产生的开口中生长栅极结构。 在栅极结构完成之后，对所形成的结构的表面进行抛光并除去TEOS的剩余层。 现在可以执行源极和漏极区域植入，使用倾斜植入物植入LDD区域。 这种倾斜的植入物渗透在所产生的栅极结构的主体下面，从而形成LDD区域。 TEOS层的去除留下了栅极结构，一个这样的结构位于衬底的表面的有源区域中，在STI区域的表面上产生了两个另外的结构。

公开(公告)号：US06300251B1

公开(公告)日：2001-10-09

申请号：US09501967

申请日：2000-02-10

申请人： Yelehanka Ramachandramurthy Pradeep ,  Vijakomar Chhagan ,  Henry Gerung

发明人： Yelehanka Ramachandramurthy Pradeep ,  Vijakomar Chhagan ,  Henry Gerung

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for anisotropically etching a partially manufactured semiconductor structure, more specifically, a stacked FET gate structure containing a bottom anti-reflective coating (Barc) layer is described. The structure is covered with a photoresist layer which is patterned to defines the gate region. The processing chemistry is predominantly carbon tetrafluoride, (CF4) with the inclusion of chlorine (Cl2) where fluorine (F) is generated in the plasma as the etchant for the structure. During processing, the wafer is cooled with helium (He) that lowers the wafer temperature and promotes sidewall deposition from the fluorine species which acts as a passivation layer producing a anisotropic or vertical etch profile. The process reduces etch time and results in very repeatable end point control of the Bark etch and poly cap etch improving the control of the structure critical dimensions and improving process throughput. The reduction in the use of fluorine based species reduces any potential environmental impact.

摘要翻译： 描述了用于各向异性蚀刻部分制造的半导体结构的方法，更具体地，描述了包含底部抗反射涂层（Barc）层的层叠FET栅极结构。 该结构被图案化以限定栅极区域的光致抗蚀剂层覆盖。 处理化学主要是四氟化碳（CF4），其包含氯（Cl2），其中在等离子体中产生氟（F）作为结构的蚀刻剂。 在处理过程中，用氦（氦）冷却晶片，从而降低晶片温度并促进作为钝化层的氟物质的侧壁沉积，产生各向异性或垂直蚀刻轮廓。 该方法减少蚀刻时间，并导致巴克蚀刻和聚盖蚀刻的非常可重复的终点控制，从而改善结构关键尺寸的控制并提高工艺流程。 氟类物质的使用减少减少了任何潜在的环境影响。

公开(公告)号：US06277700B1

公开(公告)日：2001-08-21

申请号：US09480272

申请日：2000-01-11

申请人： Jie Yu ,  Guan Ping Wu ,  Yelehanka Ramachandramurthy Pradeep

发明人： Jie Yu ,  Guan Ping Wu ,  Yelehanka Ramachandramurthy Pradeep

IPC分类号： H01L21336

CPC分类号： H01L21/31116

摘要： A method of etching silicon nitride spacers beside a gate structure comprising: providing a gate electrode over a gate oxide layer on a substrate. A liner oxide layer is provided over the substrate and the gate electrode. A silicon nitride layer is provided over the liner oxide layer. The invention's nitride etch recipe is performed in a plasma etcher to anisotropically etch the silicon nitride layer to create spacers. The nitride etch recipe comprises a main etch step and an over etch step. The main etch step comprises the following conditions: a Cl2 flow between 35 and 55 molar %, a He flow between 35 and 55 molar %, a backside He pressure between 4 and 10 torr; and a HBr flow between 7.5 and 12.5 molar %; a pressure between 400 to 900 mTorr; at a power between 300 and 600 Watts. The etch recipe provides a spacer width to nitride layer thickness ratio of about 1:1 and does not pit the Si substrate surface.

摘要翻译： 一种在栅极结构旁边蚀刻氮化硅间隔物的方法，包括：在衬底上的栅氧化层上提供栅电极。 衬底氧化物层设置在衬底和栅电极之上。 在衬垫氧化物层上提供氮化硅层。 本发明的氮化物蚀刻配方在等离子体蚀刻器中进行，以各向异性地蚀刻氮化硅层以产生间隔物。 氮化物蚀刻配方包括主蚀刻步骤和过蚀刻步骤。 主蚀刻步骤包括以下条件：在35和55摩尔％之间的Cl 2流动，He流动在35和55摩尔％之间，背面He压力在4和10托之间; 7.5至12.5摩尔％的HBr流量; 压力在400至900 mTorr之间; 功率在300至600瓦之间。 蚀刻配方提供了约1：1的间隔物宽度与氮化物层厚度比，并且不会沉积Si衬底表面。

公开(公告)号：US06277683B1

公开(公告)日：2001-08-21

申请号：US09514900

申请日：2000-02-28

申请人： Yelehanka Ramachandramurthy Pradeep ,  Henry Gerung ,  Jie Yu ,  Pei Ching Lee

发明人： Yelehanka Ramachandramurthy Pradeep ,  Henry Gerung ,  Jie Yu ,  Pei Ching Lee

IPC分类号： H01L218238

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665

摘要： A process for forming salicided CMOS devices, and non-salicide CMOS devices, on the same semiconductor substrate, using only one silicon nitride layer to provide a component for a composite spacer on the sides of the salicided CMOS devices, and to provide a blocking shape during metal silicide formation, for the non-salicided CMOS devices, has been developed. The process features the use of a disposable organic spacer, on the sides of polysilicon gate structures, used to define the heavily doped source/drain regions, for all CMOS devices. A silicon nitride layer, obtained via LPCVD procedures, at a temperature between 800 to 900° C., is then deposited and patterned to provide the needed spacer, on the sides of the CMOS devices experiencing the salicide process, while the same silicon nitride layer is used to provide the blocking shape needed to prevent metal suicide formation for the non-salicided CMOS devices.

摘要翻译： 在相同的半导体衬底上形成水化CMOS器件和非硅化物半导体器件的方法，其仅使用一个氮化硅层来提供用于复合间隔物的部件用于在水化CMOS器件的侧面，并提供阻挡形状 在金属硅化物形成期间，对于非水银CMOS器件，已经开发出来。 该方法的特征在于，对于所有CMOS器件，在多晶硅栅极结构的侧面上使用用于限定重掺杂源极/漏极区域的一次性有机间隔物。 然后在800至900℃的温度下通过LPCVD方法获得的氮化硅层被沉积和图案化以在经历自对准硅化物工艺的CMOS器件的侧面上提供所需的间隔物，而同一氮化硅层 用于提供防止非水银CMOS器件形成金属硅化所需的阻挡形状。

公开(公告)号：US06248006B1

公开(公告)日：2001-06-19

申请号：US09490155

申请日：2000-01-24

申请人： Madhusudan Mukhopadhyay ,  Subramanian Balakumar ,  Chivukula Subrahmanyam ,  Yelehanka Ramachandramurthy Pradeep

发明人： Madhusudan Mukhopadhyay ,  Subramanian Balakumar ,  Chivukula Subrahmanyam ,  Yelehanka Ramachandramurthy Pradeep

IPC分类号： B24B508

CPC分类号： B24B37/20 ,  B24B37/26 ,  B24B57/02

摘要： A new apparatus is provided that allows for uniform polishing of semiconductor surfaces. The single polishing pad of conventional CMP methods is divided into a split pad, the split pad allows for separate adjustments of CMP control parameters across the surface of the wafer. These adjustments can extend from the center of the wafer to its perimeter (along the radius of the wafer) thereby allowing for the elimination of conventional problems of non-uniformity of polishing between the center of the surface that is polished and the perimeter of the surface that is polished.

摘要翻译： 提供了允许半导体表面的均匀抛光的新设备。 传统CMP方法的单个抛光垫被分成分裂垫，分离垫允许跨晶片表面的CMP控制参数的单独调整。 这些调整可以从晶片的中心延伸到其周边（沿着晶片的半径），从而可以消除抛光表面的中心与表面周边之间的抛光不均匀的常规问题 那是抛光。

公开(公告)号：US5866448A

公开(公告)日：1999-02-02

申请号：US902757

申请日：1997-07-30

申请人： Yelehanka Ramachandramurthy Pradeep ,  Tang Kok Hiang ,  Mei Sheng Zhou

发明人： Yelehanka Ramachandramurthy Pradeep ,  Tang Kok Hiang ,  Mei Sheng Zhou

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  Y10S438/963

摘要： A method for fabrication of a lightly-doped-drain (LDD) structure for self aligned polysilicon gate MOSFETs is described wherein a polymer layer, formed along the sidewall during the patterning process of the polysilicon gate electrode, is used to mask the source/drain ion implant. The sidewall polymer layer replaces the conventional silicon oxide sidewall as an LDD spacer and offers improved thickness control as well as an improved sequence of processing steps whereby the deposition of a spacer oxide layer onto the gate oxide is eliminated. A cap oxide layer first deposited over the gate polysilicon layer. This oxide layer is then patterned and etched using RIE under conditions which form a polymer sidewall layer along the edges of the cap oxide pattern. The polysilicon layer is then etched, and has a pattern concentric with the cap oxide pattern but wider by the thickness of the polymer sidewall. After removal of the polymer and residual photoresist, the source/drain implant is performed, followed by removal of the polysilicon lip by RIE using the cap oxide as a mask. The LDD implant is then performed.

摘要翻译： 描述了一种制造用于自对准多晶硅栅极MOSFET的轻掺杂漏极（LDD）结构的方法，其中在多晶硅栅电极的图案化工艺期间沿侧壁形成的聚合物层用于掩蔽源/漏 离子植入。 侧壁聚合物层代替常规的氧化硅侧壁作为LDD间隔物，并提供改进的厚度控制以及改进的处理步骤顺序，从而消除间隔氧化物层沉积到栅极氧化物上。 首先沉积在栅极多晶硅层上的覆盖氧化物层。 然后使用RIE在沿着氧化物图案的边缘形成聚合物侧壁层的条件下对该氧化物层进行构图和蚀刻。 然后蚀刻多晶硅层，并且具有与盖氧化物图案同心的图案，但是通过聚合物侧壁的厚度更宽。 在去除聚合物和残余光致抗蚀剂之后，进行源极/漏极注入，随后通过RIE使用帽氧化物作为掩模去除多晶硅唇缘。 然后执行LDD植入。