公开(公告)号：US6151245A

公开(公告)日：2000-11-21

申请号：US215650

申请日：1998-12-17

Applicant: Federico Pio ,  Nicola Zatelli ,  Laurent Sourgen ,  Mathieu Lisart

Inventor： Federico Pio ,  Nicola Zatelli ,  Laurent Sourgen ,  Mathieu Lisart

IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC classification number: H01L27/115 ,  H01L27/02

Abstract: An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

Abstract translation: EEPROM单元被描述为具有在第一金属层中优选形成的屏蔽金属结构，并且在浮动栅极端子处基本上覆盖关系。 这样可以通过测量浮栅端子上的电荷量来获得异常读数的可能性。 可以提供要在第三和随后的金属层中形成的另外的筛选金属结构，以完全覆盖电池并提供额外的防止异常读数的保护。

公开(公告)号：US5793673A

公开(公告)日：1998-08-11

申请号：US914518

申请日：1997-08-19

Applicant: Federico Pio ,  Carlo Riva

Inventor： Federico Pio ,  Carlo Riva

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34 ,  H01L29/68

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A method for programming a two-level polysilicon EEPROM memory cell, which cell is implemented in MOS technology on a semiconductor substrate and comprises a floating gate transistor and a further control gate overlying the floating gate with a dielectric layer therebetween, provides for the application of a negative voltage to the control gate during the cell write phase. This enables the voltages being applied across the thin tunnel oxide layer to be distributed so as to reduce the maximum amount of energy of the "holes" and improve the oxide reliability. In addition, by controlling the rise speed of the impulse to the drain region during the write phase, and of the impulse to the control gate during the erase phase, the maximum current flowing through the tunnel oxide can be set and the electric field being applied to the tunnel oxide kept constant, thereby the device life span can be extended.

Abstract translation: 一种用于编程两电平多晶硅EEPROM存储单元的方法，该单元在半导体衬底上的MOS技术中实现，并且包括浮置栅晶体管和覆盖浮置栅极的其它控制栅极，其间具有介电层， 在单元写入阶段期间向控制栅极施加负电压。 这使得施加在薄隧道氧化物层上的电压被分布，以便减少“孔”的最大能量并提高氧化物的可靠性。 此外，通过在写入阶段期间控制到漏极区域的脉冲的上升速度以及在擦除阶段期间对控制栅极的脉冲的上升速度，可以设定流过隧道氧化物的最大电流并施加电场 隧道氧化物保持恒定，从而可延长设备使用寿命。

公开(公告)号：US5659501A

公开(公告)日：1997-08-19

申请号：US639931

申请日：1996-04-26

Applicant: Livio Baldi ,  Federico Pio

Inventor： Livio Baldi ,  Federico Pio

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C11/34

CPC classification number: G11C16/30 ,  G11C16/12

Abstract: A programming voltage is supplied to a control gate of a non-volatile memory cell via a control gate line. A supply voltage is coupled to a first plate of a capacitor and a reference voltage is coupled to a second plate of the capacitor. The supply voltage is then uncoupled from the first plate and the reference voltage is uncoupled from the second plate. Next, the reference voltage is coupled to the first plate to generate the programming voltage on the second plate.

Abstract translation: 编程电压通过控制栅极线提供给非易失性存储单元的控制栅极。 电源电压耦合到电容器的第一板，参考电压耦合到电容器的第二板。 然后将电源电压与第一板分离，并且参考电压与第二板脱离。 接下来，参考电压耦合到第一板以在第二板上产生编程电压。

公开(公告)号：US5528536A

公开(公告)日：1996-06-18

申请号：US344232

申请日：1994-11-23

Applicant: Livio Baldi ,  Federico Pio

Inventor： Livio Baldi ,  Federico Pio

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C5/14

CPC classification number: G11C16/30 ,  G11C16/12

Abstract: A programming voltage is supplied to a control gate of a non-volatile memory cell via a control gate line. A supply voltage is coupled to a first plate of a capacitor and a reference voltage is coupled to a second plate of the capacitor. The supply voltage is then uncoupled from the first plate and the reference voltage is uncoupled from the second plate. Next, the reference voltage is coupled to the first plate to generate the programming voltage on the second plate.

Abstract translation: 编程电压通过控制栅极线提供给非易失性存储单元的控制栅极。 电源电压耦合到电容器的第一板，参考电压耦合到电容器的第二板。 然后将电源电压与第一板分离，并且参考电压与第二板脱离。 接下来，参考电压耦合到第一板以在第二板上产生编程电压。

公开(公告)号：US5367483A

公开(公告)日：1994-11-22

申请号：US983799

申请日：1992-11-24

Applicant: Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

Inventor： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC: G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  H01L21/70

CPC classification number: H01L27/11521 ,  H01L27/11558

Abstract: A method for producing electrically erasable and programmable read-only memory cells with a single polysilicon level, including the use of a sacrificial layer of silicon oxide to produce a high-thickness silicon oxide layer on the active area. The active area of the cell is protected from heavy source and drain implantation in order to improve reliability.

Abstract translation: 一种用于制造具有单个多晶硅级别的电可擦除和可编程只读存储器单元的方法，包括使用氧化硅牺牲层在有源区上产生高厚度氧化硅层。 为了提高可靠性，保护电池的有源区域免受重的源极和漏极注入。

公开(公告)号：US10114746B2

公开(公告)日：2018-10-30

申请号：US12904807

申请日：2010-10-14

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G06F12/06 ,  G06F12/02 ,  G06F3/06

Abstract: Nonvolatile storage includes first and second memory types with different read latencies. FLASH memory and phase change memory are examples. A first portion of a data block is stored in the phase change memory and a second portion of the data block is stored in the FLASH memory. The first portion of the data block is accessed prior to the second portion of the data block during a read operation.

公开(公告)号：US08729523B2

公开(公告)日：2014-05-20

申请号：US13600777

申请日：2012-08-31

Applicant: Federico Pio

Inventor： Federico Pio

IPC: H01L29/06

CPC classification number: H01L45/16 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/249 ,  H01L29/41758 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

Abstract: Three dimensional memory array architectures and methods of forming the same are provided. An example memory array can include a stack comprising a plurality of first conductive lines at a number of levels separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension. The at least one conductive extension, storage element material, and cell select material are located between co-planar pairs of the plurality of first conductive lines.

Abstract translation: 提供三维存储器阵列结构及其形成方法。 示例性存储器阵列可以包括堆叠，其包括通过至少绝缘材料彼此分开的多个级别的多个第一导电线，以及布置成基本上垂直于多个第一导电线延伸的至少一个导电延伸部。 存储元件材料围绕至少一个导电延伸部形成。 细胞选择材料形成在至少一个导电延伸部周围。 所述至少一个导电延伸部，存储元件材料和电池选择材料位于所述多个第一导电线的共面对之间。

公开(公告)号：US20140061574A1

公开(公告)日：2014-03-06

申请号：US13600699

申请日：2012-08-31

Applicant: Federico Pio

Inventor： Federico Pio

IPC: H01L45/00 ,  H01L21/8239

CPC classification number: H01L45/06 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/101 ,  H01L27/224 ,  H01L27/2427 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

Abstract: Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.

Abstract translation: 提供三维记忆阵列及其形成方法。 示例性三维存储器阵列可以包括堆叠，其包括通过至少绝缘材料彼此分开的多个第一导电线，以及布置成基本上垂直于多个第一导电线延伸的至少一个导电延伸部，使得 至少一个导电延伸部与多个第一导线中的至少一个的一部分相交。 存储元件材料围绕至少一个导电延伸部形成。 细胞选择材料形成在至少一个导电延伸部周围。

公开(公告)号：US20080049521A1

公开(公告)日：2008-02-28

申请号：US11844480

申请日：2007-08-24

Applicant: Rino Micheloni ,  Luca Crippa ,  Roberto Ravasio ,  Federico Pio

Inventor： Rino Micheloni ,  Luca Crippa ,  Roberto Ravasio ,  Federico Pio

IPC: G11C16/04

CPC classification number: G11C16/344

Abstract: A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

Abstract translation: 一种用于操作闪存设备的方法。 存储器件包括存储器单元矩阵，每个存储器单元具有限定存储在存储器单元中的值的可编程阈值电压。 该方法包括以下步骤：擦除存储器单元块，以及在预定的压缩范围内压缩块的存储单元的阈值电压，其中压缩步骤包括：选择块写入的至少一个第一存储单元 目标值 将块的存储器单元的子集的阈值电压恢复到压缩范围，该子集包括与至少一个第一存储器相邻的块的至少一个第一存储器单元和/或至少一个第二存储器单元 细胞; 并且至少部分地将目标值写入至少一个第一存储单元。

公开(公告)号：US20060209594A1

公开(公告)日：2006-09-21

申请号：US11367707

申请日：2006-03-02

Applicant: Federico Pio ,  Efrem Bolandrina ,  Daniele Vimercati

Inventor： Federico Pio ,  Efrem Bolandrina ,  Daniele Vimercati

IPC: G11C16/04

CPC classification number: G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

Abstract: A memory device includes a plurality of memory cells and a comparison circuit that compares a set of selected memory cells with at least one reference cell having a threshold voltage. The comparison circuit includes a bias circuit that applies a biasing voltage having a substantially monotone time pattern to the selected memory cells and to the at least one reference cell, sense amplifiers that detect the reaching of a comparison current by a cell current of each selected memory cell and by a reference current of each reference cell, a logic unit that determines a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and by the at least one reference current, and a time shift structure that time shifts at least one of said detections according to at least one predefined interval to emulate the comparison with at least one further reference cell having a further threshold voltage.

Abstract translation: 存储器件包括多个存储器单元和比较电路，其将所选择的存储器单元组与至少一个具有阈值电压的参考单元进行比较。 比较电路包括偏置电路，该偏置电路将具有基本上单调的时间图案的偏置电压施加到所选择的存储器单元和至少一个参考单元，检测放大器，其通过每个选择的存储器的单元电流检测比较电流的到达 单元和每个参考单元的参考电流;逻辑单元，其根据比较电流到达相应的单元电流和至少一个参考电流的时间关系来确定每个选择的存储单元的状态;以及 时移结构，其根据至少一个预定间隔时间移动至少一个所述检测，以模拟与具有另一阈值电压的至少一个另外的参考小区的比较。