公开(公告)号：US6151245A

公开(公告)日：2000-11-21

申请号：US215650

申请日：1998-12-17

申请人： Federico Pio ,  Nicola Zatelli ,  Laurent Sourgen ,  Mathieu Lisart

发明人： Federico Pio ,  Nicola Zatelli ,  Laurent Sourgen ,  Mathieu Lisart

IPC分类号： G11C16/02 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC分类号： H01L27/115 ,  H01L27/02

摘要： An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

摘要翻译： EEPROM单元被描述为具有在第一金属层中优选形成的屏蔽金属结构，并且在浮动栅极端子处基本上覆盖关系。 这样可以通过测量浮栅端子上的电荷量来获得异常读数的可能性。 可以提供要在第三和随后的金属层中形成的另外的筛选金属结构，以完全覆盖电池并提供额外的防止异常读数的保护。

公开(公告)号：US5889720A

公开(公告)日：1999-03-30

申请号：US852104

申请日：1997-05-06

申请人： Mathieu Lisart ,  Laurent Sourgen

发明人： Mathieu Lisart ,  Laurent Sourgen

IPC分类号： G11C16/12 ,  H03K4/00 ,  G11C13/00

CPC分类号： H03K4/00 ,  G11C16/12

摘要： To form a ramp signal for the programming of a memory cell without losing excess voltage in a control circuit, the output of a voltage pull-up circuit is connected to the programming input using a P type transistor. It is shown that this P type transistor then charges the memory array at constant current, prompting a linear increase of the voltage. This results in preventing the memory cell that is to be programmed from being subjected to excessively sudden variations of voltage. It is shown that by acting in this way, the integrated circuit can be made to work even with very low voltages.

摘要翻译： 为了形成用于编程存储器单元的斜坡信号，而不会在控制电路中损失过多的电压，使用P型晶体管将电压上拉电路的输出连接到编程输入。 这表明该P型晶体管然后以恒定电流对存储器阵列充电，促使电压线性增加。 这导致防止被编程的存储单元经受过度突然的电压变化。 显示出通过这样的方式，即使在非常低的电压下也可以使集成电路工作。

公开(公告)号：US5384749A

公开(公告)日：1995-01-24

申请号：US96687

申请日：1993-07-23

申请人： Mathieu Lisart ,  Laurent Sourgen

发明人： Mathieu Lisart ,  Laurent Sourgen

IPC分类号： G06F3/08 ,  G06F12/00 ,  G06F12/02 ,  G06F12/14 ,  G06F21/02 ,  G06K19/073 ,  G07F7/10 ,  G11C7/24 ,  G11C8/04 ,  G11C16/02 ,  G11C17/00 ,  G11C11/40

CPC分类号： G11C8/04 ,  G06F12/1441 ,  G06Q20/341 ,  G06Q20/35765 ,  G07F7/1008 ,  G11C7/24

摘要： In a memory, a zone descriptor contains authorizations to act which may pertain to actions of reading, writing and erasure and which concerns memory words of a zone of the memory controlled by this descriptor. The zone descriptor also has an information element indicating the length of the memory zone by including the address of the next descriptor. An internal zone control signal is produced in order to store a mode of management of the memory zone and, an address corresponding to the end of the zone. The end of zone address is then compared with the addresses delivered by an address counter. A modification of the stored information is prompted when the end of a zone is reached.

摘要翻译： 在存储器中，区域描述符包含作用的授权，其可以涉及读取，写入和擦除的动作，并且涉及由该描述符控制的存储器区域的存储器字。 区域描述符还具有通过包括下一描述符的地址来指示存储区的长度的信息元素。 产生内部区域控制信号，以便存储存储器区域的管理模式以及对应于该区域的结尾的地址。 然后将区域地址的结束与由地址计数器传递的地址进行比较。 当到达区域的末尾时，将提示存储的信息的修改。

公开(公告)号：US5978915A

公开(公告)日：1999-11-02

申请号：US573942

申请日：1995-12-18

申请人： Mathieu Lisart ,  Laurent Sourgen

发明人： Mathieu Lisart ,  Laurent Sourgen

IPC分类号： G06F12/14 ,  G06F21/02 ,  G06K17/00 ,  G06F11/00 ,  G11C17/00

CPC分类号： G06F12/1425

摘要： The access to memory words of an integrated circuit is protected by the creation of a decision table that receives addresses of instruction words and/or data words to be protected and that receives also addresses of the control bits of a control word assigned to a word to be protected. It can be shown that this mode of action provides greater security through the use of a decision table made in wired circuit form as well as greater flexibility through the programmable quality of the control words assigned to each memory word to be controlled.

摘要翻译： 通过创建接收要保护的指令字和/或数据字的地址的决定表来保护对集成电路的存储字的访问，并且还接收分配给一个字的控制字的控制位的地址 被保护。 可以看出，这种操作模式通过使用以有线电路形式制定的决策表以及通过分配给要控制的每个存储器字的控制字的可编程质量而具有更大的灵活性来提供更大的安全性。

公开(公告)号：US08532947B2

公开(公告)日：2013-09-10

申请号：US12969266

申请日：2010-12-15

申请人： Pascal Fornara ,  Mathieu Lisart

发明人： Pascal Fornara ,  Mathieu Lisart

IPC分类号： G01R19/00 ,  G06F19/00

CPC分类号： G06K19/067 ,  H01L23/48 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2223/54446 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes non-volatile storage configured to secretly store a digital word, the value of which forms an identification code. The integrated circuit also includes control circuitry configured to receive the digital word and to generate transient electrical currents or transient voltages, the characteristics of which depend on the value of the digital word. There is an electrically conductive network configured to be passed through by the electrical currents or receive the transient voltages so as to generate an electromagnetic field that identifies the integrated circuit.

摘要翻译： 集成电路包括被配置为秘密地存储数字字的非易失性存储器，其数值字形成识别码。 集成电路还包括配置成接收数字字并产生瞬态电流或瞬态电压的控制电路，其特性取决于数字字的值。 存在导电网络，其配置为通过电流通过或接收瞬态电压，以便产生识别集成电路的电磁场。

公开(公告)号：US6147521A

公开(公告)日：2000-11-14

申请号：US876282

申请日：1997-06-12

申请人： Hubert Degoirat ,  Mathieu Lisart

发明人： Hubert Degoirat ,  Mathieu Lisart

IPC分类号： G01R19/165 ,  H03K5/153 ,  H03K3/037

CPC分类号： G01R19/1659 ,  G01R19/16519

摘要： The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

公开(公告)号：US5859526A

公开(公告)日：1999-01-12

申请号：US871096

申请日：1997-06-06

申请人： Tien-Dung Do ,  Mathieu Lisart

发明人： Tien-Dung Do ,  Mathieu Lisart

IPC分类号： G05F3/24 ,  G11C5/14 ,  G05F1/40

CPC分类号： G11C5/147 ,  G05F3/242

摘要： A voltage reference generator includes a voltage source and a differential amplifier. The voltage source supplies a stable voltage reference to a positive input of the differential amplifier which is configured as a follower having its output looped back to its negative input. The negative feedback loop is a variable-resistance loop that is controlled by the output of the differential amplifier. The variable-resistance feedback loop transiently imposes open-loop operation when the voltage reference generator is turned on so as to provide high current to the output before imposing closed-loop operation in follower mode.

摘要翻译： 电压基准发生器包括电压源和差分放大器。 电压源为差分放大器的正输入提供稳定的参考电压，差分放大器的正输入被配置为具有循环回到其负输入的引导器。 负反馈回路是由差分放大器的输出控制的可变电阻回路。 当电压基准发生器导通时，可变电阻反馈环路瞬时施加开环操作，以便在跟随器模式下施加闭环操作之前向输出端提供高电流。

公开(公告)号：US07388802B2

公开(公告)日：2008-06-17

申请号：US11423852

申请日：2006-06-13

申请人： Sylvie Wuidart ,  Mathieu Lisart ,  Nicolas Demange

发明人： Sylvie Wuidart ,  Mathieu Lisart ,  Nicolas Demange

IPC分类号： G11C8/00 ,  G11C5/06 ,  G11C7/00 ,  G11C8/02 ,  G06F12/00

CPC分类号： G11C8/20 ,  G11C7/24 ,  G11C16/22

摘要： A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.

摘要翻译： 存储器包括布置在存储器阵列中的存储单元，以及地址解码器，用于根据应用于存储器的读取地址将存储单元选择信号应用于存储器阵列。 存储器包括地址重构电路，其从存储器单元选择信号重建读取地址的至少一部分，并且提供能够检测影响选择信号的错误注入的第一重建地址。 特别但不排他地适用于芯片卡的集成电路。

公开(公告)号：US5500601A

公开(公告)日：1996-03-19

申请号：US839618

申请日：1992-02-21

申请人： Mathieu Lisart ,  Richard Fournel

发明人： Mathieu Lisart ,  Richard Fournel

IPC分类号： G01D5/16 ,  G01D5/18 ,  G06F1/00 ,  G06F21/55 ,  G11C16/28 ,  G01R27/08 ,  G01R31/26 ,  G11C29/00

CPC分类号： G06F21/558 ,  G01D5/16 ,  G01D5/18 ,  G11C16/28 ,  G06F2207/7219

摘要： The invention is a device to detect the logic state of a component whose impedance depends on this state, the device including means to generate a current and a measurement voltage so that the current consumption remains constant during cell detection regardless of the state detected, the device also including means to detect the logic state of the component.

摘要翻译： 本发明是一种用于检测其阻抗取决于该状态的部件的逻辑状态的装置，该装置包括产生电流和测量电压的装置，使得在小区检测期间电流消耗保持恒定，而与检测到的状态无关，该装置 还包括检测组件的逻辑状态的方法。

公开(公告)号：US09323941B2

公开(公告)日：2016-04-26

申请号：US12942557

申请日：2010-11-09

申请人： Fabrice Marinet ,  Mathieu Lisart

发明人： Fabrice Marinet ,  Mathieu Lisart

IPC分类号： G06F11/30 ,  G06F12/14 ,  H04L29/06 ,  G06F21/62 ,  G06F21/78 ,  G06F11/14 ,  G06F21/77

CPC分类号： H04L9/088 ,  G06F3/0623 ,  G06F3/0644 ,  G06F3/0688 ,  G06F11/1458 ,  G06F12/1408 ,  G06F21/62 ,  G06F21/77 ,  G06F21/78 ,  G06F2212/402

摘要： The component comprises a first memory (MM) comprising a first portion (P1) having a content modified with a first modification entity (K1) and a second portion (P2) having a content modified with a second entity (K2), a storage means (MS) configured to store the first entity (K1) secretly, a non-volatile memory (NVM) storing an item of entity information representative of the second entity (K2) in a location (END) designated by a first indication (INDK2) contained in the said first portion of the first memory.

摘要翻译： 该组件包括第一存储器（MM），其包括具有由第一修改实体（K1）修改的内容的第一部分（P1）和具有用第二实体（K2）修改的内容的第二部分（P2），存储装置 （MS）被配置为秘密地存储第一实体（K1），非易失性存储器（NVM）将代表第二实体（K2）的实体信息项存储在由第一指示（INDK2）指定的位置（END）中， 包含在第一存储器的所述第一部分中。