公开(公告)号：US08728891B2

公开(公告)日：2014-05-20

申请号：US13560091

申请日：2012-07-27

申请人： Heimo Hofer ,  Martin Poelzl

发明人： Heimo Hofer ,  Martin Poelzl

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/3086 ,  H01L21/31144 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78642

摘要： Contact openings are produced in a semiconductor body by forming a plurality of self-aligned structures on a main surface of a semiconductor body, each self-aligned structure filling a trench formed in the semiconductor body and extending above and onto the main surface. Adjacent ones of the self-aligned structures have spaced apart sidewalls which face each other. A spacer layer is formed on the sidewalls of the self-aligned structures. Openings are formed in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures. Each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer. Self-aligned contact structures can also be produced on a semiconductor body, with or without using the spacer layer.

摘要翻译： 通过在半导体主体的主表面上形成多个自对准结构，在半导体本体中产生接触开口，每个自对准结构填充形成在半导体本体中并在主表面上方并延伸到主表面上的沟槽。 相邻的自对准结构具有彼此面对的间隔开的侧壁。 间隔层形成在自对准结构的侧壁上。 在相邻的自对准结构之间的半导体本体中形成开口，而间隔层位于自对准结构的侧壁上。 每个开口具有对应于间隔层的厚度的相邻沟槽的侧壁的宽度和距离。 自对准的接触结构也可以在具有或不使用间隔层的半导体本体上产生。

公开(公告)号：US20130181284A1

公开(公告)日：2013-07-18

申请号：US13350987

申请日：2012-01-16

申请人： Martin Poelzl

发明人： Martin Poelzl

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/302

CPC分类号： H01L29/66348 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/76897 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/6634 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A method for producing a semiconductor component is described. The method includes providing a semiconductor body having a first surface and being comprised of a first semiconductor material extending to the first surface. At least one trench extends from the first surface into the semiconductor body and includes a gate electrode insulated from the semiconductor body and arranged below the first surface. The method further includes: forming a second insulation layer on the first surface with a recess that overlaps in projection onto the first surface with the conductive region; forming a mask region in the recess; etching the second insulation layer selectively to the mask region and the semiconductor body to expose the semiconductor body at the first surface; depositing a third insulation layer on the first surface; and etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the a least one trench is exposed at the first surface.

摘要翻译： 对半导体元件的制造方法进行说明。 该方法包括提供具有第一表面并且包括延伸到第一表面的第一半导体材料的半导体本体。 至少一个沟槽从第一表面延伸到半导体本体中，并且包括与半导体本体绝缘并布置在第一表面下方的栅电极。 所述方法还包括：在所述第一表面上形成第二绝缘层，所述第二绝缘层具有与所述导电区域在所述第一表面上的突出部重叠的凹部; 在所述凹部中形成掩模区域; 将所述第二绝缘层选择性地蚀刻到所述掩模区域和所述半导体本体以在所述第一表面处露出所述半导体本体; 在第一表面上沉积第三绝缘层; 以及蚀刻所述第三绝缘层，使得布置在所述至少一个沟槽旁边的所述半导体本体的半导体台面在所述第一表面处露出。

公开(公告)号：US08487370B2

公开(公告)日：2013-07-16

申请号：US12847537

申请日：2010-07-30

申请人： Oliver Blank ,  Ralf Siemieniec ,  Martin Poelzl ,  Maximilian Roesch

发明人： Oliver Blank ,  Ralf Siemieniec ,  Martin Poelzl ,  Maximilian Roesch

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66727 ,  H01L29/66734

摘要： A semiconductor device includes a semiconductor body including a trench with first and second opposing sidewalls. A first electrode is arranged in a lower portion of the trench and a second electrode in an upper portion of the trench. A dielectric structure is arranged in the trench, including a first portion between the electrodes. The first portion includes, in sequence along a lateral direction from the first sidewall to the second sidewall, a first part including a first dielectric material, a second part including a second dielectric material selectively etchable to the first dielectric material, a third part including the first dielectric material, the first dielectric material of the third part being continuously arranged along a vertical direction from a top side of the first electrode to a bottom side of the second electrode, a fourth part including the second dielectric material and a fifth part including the first dielectric material.

摘要翻译： 半导体器件包括半导体本体，其包括具有第一和第二相对侧壁的沟槽。 第一电极布置在沟槽的下部，沟槽的上部设有第二电极。 电介质结构布置在沟槽中，包括电极之间的第一部分。 第一部分沿着从第一侧壁到第二侧壁的横向方向依次包括第一部分，包括第一介电材料，第二部分包括可选择性地蚀刻到第一电介质材料的第二介电材料，第三部分包括第 第一电介质材料，第三部分的第一介电材料沿着垂直方向从第一电极的顶侧到第二电极的底侧连续地布置，第四部分包括第二电介质材料，第五部分包括第 第一介电材料。

公开(公告)号：US08313995B2

公开(公告)日：2012-11-20

申请号：US13005694

申请日：2011-01-13

申请人： Martin Poelzl

发明人： Martin Poelzl

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811

摘要： A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括提供具有水平表面的半导体本体。 在水平面上形成外延硬掩模。 通过在水平表面上相对于外延硬掩模的选择性外延形成外延区域，使得外延区域被调整到外延硬掩模。 在半导体本体中形成垂直沟槽。 绝缘场板形成在垂直沟槽的下部，绝缘栅电极形成在绝缘场板的上方。 此外，提供了一种用于形成场效应半导体器件的方法。

公开(公告)号：US20110095360A1

公开(公告)日：2011-04-28

申请号：US12605933

申请日：2009-10-26

申请人： Joachim Krumrey ,  Gerhard Noebauer ,  Martin Poelzl ,  Marc Probst

发明人： Joachim Krumrey ,  Gerhard Noebauer ,  Martin Poelzl ,  Marc Probst

IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811

摘要： A transistor component and method of forming a transistor component. One embodiment provides a semiconductor arrangement including a semiconductor body having a at least one first trench, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric. A dielectric layer is formed on the first field electrode in the at least one first trench, including depositing a dielectric material on a first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench.

摘要翻译： 晶体管元件及形成晶体管元件的方法。 一个实施例提供一种半导体装置，其包括半导体本体，该半导体本体具有至少一个第一沟槽，第一场电极，布置在至少一个第一沟槽的下沟槽部分中，并且通过场电极电介质与半导体本体绝缘。 在所述至少一个第一沟槽中的所述第一场电极上形成电介质层，包括在所述半导体主体的第一侧和所述场板上以比所述至少一个第一沟槽的侧壁更高的沉积速率沉积介电材料 沟。

公开(公告)号：US20100270612A1

公开(公告)日：2010-10-28

申请号：US12834000

申请日：2010-07-11

申请人： Martin Poelzl ,  Walter Rieger

发明人： Martin Poelzl ,  Walter Rieger

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7805

摘要： A method for producing a vertical transistor component includes providing a semiconductor substrate, applying an auxiliary layer to the semiconductor substrate, and patterning the auxiliary layer for the purpose of producing at least one trench which extends as far as the semiconductor substrate and which has opposite sidewalls. The method further includes producing a monocrystalline semiconductor layer on at least one of the sidewalls of the trench, producing an electrode insulated from the monocrystalline semiconductor layer on the at least one sidewall of the trench and the semiconductor substrate.

摘要翻译： 一种用于制造垂直晶体管组件的方法包括提供半导体衬底，向半导体衬底施加辅助层，并且为了产生至少一个延伸至半导体衬底并且具有相对侧壁的沟槽的目的来构图辅助层 。 该方法还包括在沟槽的至少一个侧壁上制造单晶半导体层，产生与沟槽和半导体衬底的至少一个侧壁上的单晶半导体层绝缘的电极。

公开(公告)号：US20090026531A1

公开(公告)日：2009-01-29

申请号：US11781582

申请日：2007-07-23

申请人： Martin Poelzl

发明人： Martin Poelzl

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L29/7811 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66696 ,  H01L29/66734 ,  H01L29/7813

摘要： A method for insulating a semiconducting material in a trench from a substrate, wherein the trench is formed in the substrate and comprising an upper portion and a lower portion, the lower portion being lined with a first insulating layer and filled, at least partially, with a semiconducting material, comprises an isotropic etching of the substrate and the semiconducting material, and forming a second insulating layer in the trench, wherein the second insulating layer covers, at least partially, the substrate and the semiconducting material.

摘要翻译： 一种用于从衬底绝缘的沟槽中的半导体材料的方法，其中所述沟槽形成在所述衬底中并且包括上部和下部，所述下部衬有第一绝缘层，并且至少部分地用 半导体材料包括衬底和半导体材料的各向同性蚀刻，以及在沟槽中形成第二绝缘层，其中第二绝缘层至少部分地覆盖衬底和半导体材料。

公开(公告)号：US20060141739A1

公开(公告)日：2006-06-29

申请号：US11287500

申请日：2005-11-25

申请人： Martin Poelzl

发明人： Martin Poelzl

IPC分类号： H01L21/76

CPC分类号： H01L29/66727 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66734

摘要： A method for fabricating contact holes in a semiconductor body proceeds from a structure in which: a plurality of trenches isolated from one another by mesa regions are provided in the semiconductor body, and electrodes are provided in the trenches, which electrodes are electrically insulated from the semiconductor body by a first insulation layer, and the upper ends of which electrodes are situated at a deeper level than the upper ends of the trenches. The method comprises the steps of: producing a second insulation layer by subjecting parts of the surface of the structure to a thermal oxidation process, and carrying out a planarization process in such a way that the semiconductor body is uncovered in the region of the mesa regions, and forming the contact holes in the mesa regions using the residues of the second insulation layer remaining after the planarization process as a contact hole mask.

摘要翻译： 在半导体本体中制造接触孔的方法从半导体本体中设置有多个通过台面区隔开的沟槽的结构，并且在沟槽中设置电极，这些电极与 半导体本体通过第一绝缘层，并且其上端的电极位于比沟槽的上端更深的水平。 该方法包括以下步骤：通过使结构的表面的部分经受热氧化工艺，并且以这样的方式进行平坦化处理来制造第二绝缘层，使得半导体主体在台面区域的区域中不被覆盖 并且使用在平坦化处理之后残留的第二绝缘层的残留物作为接触孔掩模，在台面区域中形成接触孔。

公开(公告)号：US20050242370A1

公开(公告)日：2005-11-03

申请号：US11027496

申请日：2004-12-30

申请人： Hans Weber ,  Gerhard Neugschwandtner ,  Martin Poelzl

发明人： Hans Weber ,  Gerhard Neugschwandtner ,  Martin Poelzl

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238

摘要： A method for producing a junction region (2, 5, 6, 7) between a trench (3) and a semiconductor zone (2) surrounding the trench (3) in a trench semiconductor device (1) has the following steps: application of an oxidation barrier layer (15) to an upper part (O) of the inner walls of the trench (3), and production of a first oxide layer (7) on a lower part (U) of the inner walls, said lower part not being covered by the oxidation barrier layer (15), by means of thermal oxidation of the uncovered (U) part of the inner walls.

摘要翻译： 在沟槽半导体器件（1）中，在沟槽（3）和围绕沟槽（3）的半导体区域（2）之间产生结区域（2,5,6,7）的方法具有以下步骤：应用 氧化阻挡层（15）到所述沟槽（3）的内壁的上部（O），以及在所述内壁的下部（U）上产生第一氧化物层（7），所述下部 不被氧化阻挡层（15）覆盖，通过内壁的未覆盖（U）部分的热氧化。