公开(公告)号：US09224610B2

公开(公告)日：2015-12-29

申请号：US13931205

申请日：2013-06-28

申请人： GLOBALFOUNDRIES, Inc.

发明人： Hoon Kim ,  Kisik Choi

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L21/28229 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes exposing a portion of a surface of a semiconductor substrate between a first spacer and a second spacer. The method further includes selectively forming a dielectric layer on the portion of the surface. A metal gate is formed over the dielectric layer and between the first spacer and the second spacer. The metal gate contacts the first spacer and the second spacer.

摘要翻译： 提供了用于制造集成电路的集成电路和方法。 根据示例性实施例，用于制造集成电路的方法包括将半导体衬底的表面的一部分暴露在第一间隔物和第二间隔物之间​​。 该方法还包括在表面的该部分上选择性地形成介电层。 金属栅极形成在电介质层之上并且在第一间隔物和第二间隔物之间​​。 金属栅极接触第一间隔物和第二间隔物。

公开(公告)号：US09178035B1

公开(公告)日：2015-11-03

申请号：US14459446

申请日：2014-08-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC分类号： H01L21/3205 ,  H01L29/66 ,  H01L21/3213

CPC分类号： H01L29/66545 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823456 ,  H01L29/4966 ,  H01L29/7833

摘要： One method of forming replacement gate structures for first and second devices, the first device being a short channel device and the second device being a long channel device, is disclosed which includes forming a first and a second gate cavity above a semiconductor substrate, the first gate cavity being narrower than the second gate cavity, forming a bulk metal layer within the first and second gate cavities, performing an etching process to recess the bulk metal layer within the first and second gate cavities, resulting in the bulk metal layer within the second gate cavity being at its final thickness, forming a masking layer over the bulk metal layer within the second gate cavity, and performing an etching process to further recess the bulk metal layer within the first gate cavity, resulting in the bulk metal layer within the first gate cavity being at its final thickness.

摘要翻译： 公开了一种形成第一和第二器件的替代栅极结构的方法，第一器件是短沟道器件，第二器件是长沟道器件，其包括在半导体衬底上形成第一和第二栅极腔，第一器件 栅极腔比第二栅极腔窄，在第一和第二栅极空腔内形成体金属层，执行蚀刻工艺以使第一和第二栅极空腔内的体金属层凹陷，导致第二栅极腔内的体金属层 栅极腔处于其最终厚度，在第二栅极腔内的体金属层上形成掩模层，并且执行蚀刻工艺以进一步使第一栅极腔内的体金属层凹陷，导致第一栅极腔内的主体金属层 门腔处于其最终厚度。

公开(公告)号：US20150255331A1

公开(公告)日：2015-09-10

申请号：US14196842

申请日：2014-03-04

申请人： GLOBALFOUNDRIES, Inc.

发明人： Xunyuan Zhang ,  Hoon Kim ,  Moosung M. Chae

IPC分类号： H01L21/768 ,  H01L23/482 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76831 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuits with copper and magnesium components and methods for producing such integrated circuits are provided. A method of producing the integrated circuits includes forming an aperture in an interlayer dielectric. A seed layer is formed in the aperture, where the seed layer includes manganese and copper, and where the seed layer has a copper concentration gradient. A core is formed overlying the seed layer, where the core includes copper.

摘要翻译： 提供了具有铜和镁组件的集成电路以及用于制造这种集成电路的方法。 集成电路的制造方法包括在层间电介质中形成孔。 在孔中形成种子层，其中种子层包括锰和铜，并且其中种子层具有铜浓度梯度。 核心覆盖种子层，其中核心包括铜。

公开(公告)号：US09076816B2

公开(公告)日：2015-07-07

申请号：US14080842

申请日：2013-11-15

申请人： GLOBALFOUNDRIES Inc.

发明人： Xunyuan Zhang ,  Xiuyu Cai ,  Hoon Kim

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/49

CPC分类号： H01L29/66545 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76856 ,  H01L21/76897 ,  H01L29/4958 ,  H01L29/6653 ,  H01L29/78

摘要： A methodology for forming a self-aligned contact (SAC) that exhibits reduced likelihood of a contact-to-gate short circuit failure and the resulting device are disclosed. Embodiments may include forming a replacement metal gate, with spacers at opposite sides thereof, on a substrate, forming a recess in an upper surface of the spacers along outer edges of the replacement metal gate, and forming an aluminum nitride (AlN) cap over the metal gate and in the recess.

摘要翻译： 公开了一种用于形成展现出接触到栅极短路故障的可能性降低的自对准接触（SAC）的方法以及所得到的器件。 实施例可以包括在衬底上形成具有相对侧面的间隔物的替换金属栅极，在替代金属栅极的外边缘上在间隔物的上表面中形成凹部，并在该金属栅极上形成氮化铝（AlN） 金属门和凹槽。

公开(公告)号：US20150179640A1

公开(公告)日：2015-06-25

申请号：US14134358

申请日：2013-12-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Hoon Kim ,  Kisik Choi ,  Jae Young Lee

IPC分类号： H01L27/088 ,  H01L21/28 ,  H01L21/265 ,  H01L21/223 ,  H01L21/8234 ,  H01L29/51

CPC分类号： H01L21/28158 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/66545

摘要： A multi-device semiconductor structure including a p-type logic device, a p-type memory device, a n-type logic device and a n-type memory device are provided on a bulk silicon substrate. Each of these devices includes a dielectric layer and either a n-type or a p-type work function layer disposed over the dielectric layer. Some of the various device types of the multi-device semiconductor structure are protected, and impurities, such as aluminum and/or nitrogen, are added to the exposed work function layers to achieve one or more other desired work functions with different threshold voltages.

摘要翻译： 包括p型逻辑器件，p型存储器件，n型逻辑器件和n型存储器件的多器件半导体结构设置在体硅衬底上。 这些器件中的每一个包括电介质层和设置在电介质层上的n型或p型功函数层。 多器件半导体结构的各种器件类型中的一些被保护，并且诸如铝和/或氮的杂质被添加到暴露的功函数层中以实现具有不同阈值电压的一个或多个其它期望的功函数。

公开(公告)号：US20150171082A1

公开(公告)日：2015-06-18

申请号：US14634222

申请日：2015-02-27

申请人： GLOBALFOUNDRIES, Inc.

发明人： Kisik Choi ,  Hoon Kim

IPC分类号： H01L27/088 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L27/088 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： Integrated circuits and methods of fabricating integrated circuits are provided herein. In an embodiment, an integrated circuit includes a first replacement gate structure, wherein the first replacement gate structure includes a layer of a high-k dielectric material and a layer of a first replacement gate fill material, and a second replacement gate structure, wherein the second replacement gate structure includes a layer of a transformed dielectric material and a layer of the replacement gate fill material.

摘要翻译： 本文提供了集成电路和制造集成电路的方法。 在一个实施例中，集成电路包括第一替代栅极结构，其中第一替换栅极结构包括高k介电材料层和第一替代栅极填充材料层以及第二替代栅极结构，其中， 第二替换栅极结构包括转换介电材料层和替代栅极填充材料层。

公开(公告)号：US09018711B1

公开(公告)日：2015-04-28

申请号：US14056144

申请日：2013-10-17

申请人： GLOBALFOUNDRIES Inc.

发明人： Xiuyu Cai ,  Hoon Kim ,  Xunyuan Zhang

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L27/092

CPC分类号： H01L27/0924 ,  H01L21/28008 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517

摘要： Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device.

摘要翻译： 公开了形成半导体器件的替代金属栅极（RMG）的方法。 具体地提供了在衬底上形成的p沟道场效应晶体管（p-FET）和n沟道场效应晶体管（n-FET），其中形成有凹部的p-FET和n-FET， 高k层和在每个凹槽内形成的阻挡层，选择性地生长在n-FET的凹槽内的功函数金属（WFM），其中高k层，势垒层和WFM各自凹入到期望的 在凹部内的高度，以及形成在每个凹部内的金属材料（例如，钨）。 通过在该方法中较早提供WFM倒角，减少了掩模材料填充到每个浇口凹槽中的风险。 此外，选择性WFM生长改善了金属材料的填充，这降低了器件中的栅极电阻。

公开(公告)号：US09012319B1

公开(公告)日：2015-04-21

申请号：US14069782

申请日：2013-11-01

申请人： GLOBALFOUNDRIES Inc.

发明人： Kisik Choi ,  Hoon Kim

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L29/51

CPC分类号： H01L21/28158 ,  H01L21/28185 ,  H01L21/28247 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545

摘要： One illustrative method disclosed herein includes removing sacrificial gate structures for NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, forming a high-k gate insulation layer in the NMOS and PMOS gate cavities, forming a lanthanide-based material layer on the high-k gate insulation layer in the NMOS and PMOS gate cavities, performing a heating process to drive material from the lanthanide-based material layer into the high-k gate insulation layer so as to thereby form a lanthanide-containing high-k gate insulation layer in each of the NMOS and PMOS gate cavities, and forming gate electrode structures above the lanthanide-containing high-k gate insulation layer in the NMOS and PMOS gate cavities.

摘要翻译： 本文公开的一种说明性方法包括去除用于NMOS和PMOS晶体管的牺牲栅极结构，从而限定NMOS和PMOS栅极空腔，在NMOS和PMOS栅极腔中形成高k栅绝缘层，在高层上形成镧系元素基材料层 -k栅极绝缘层，执行加热处理以将材料从镧系元素基材料层驱动到高k栅极绝缘层中，从而形成含镧系元素的高k栅极绝缘层 在每个NMOS和PMOS栅极腔中，以及在NMOS和PMOS栅极腔中的含镧系元素的高k栅极绝缘层之上形成栅电极结构。

公开(公告)号：US20150001643A1

公开(公告)日：2015-01-01

申请号：US13931205

申请日：2013-06-28

申请人： GlobalFoundries, Inc.

发明人： Hoon Kim ,  Kisik Choi

IPC分类号： H01L21/28 ,  H01L29/51

CPC分类号： H01L21/28229 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/28185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes exposing a portion of a surface of a semiconductor substrate between a first spacer and a second spacer. The method further includes selectively forming a dielectric layer on the portion of the surface. A metal gate is formed over the dielectric layer and between the first spacer and the second spacer. The metal gate contacts the first spacer and the second spacer.

摘要翻译： 提供了用于制造集成电路的集成电路和方法。 根据示例性实施例，用于制造集成电路的方法包括将半导体衬底的表面的一部分暴露在第一间隔物和第二间隔物之间​​。 该方法还包括在表面的该部分上选择性地形成介电层。 金属栅极形成在电介质层之上并且在第一间隔物和第二间隔物之间​​。 金属栅极接触第一间隔物和第二间隔物。

公开(公告)号：US10229855B2

公开(公告)日：2019-03-12

申请号：US15846365

申请日：2017-12-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L27/088 ,  H01L29/66

摘要： A device includes a first transistor device having a first threshold voltage and including a first gate electrode structure positioned in a first gate cavity. The first gate electrode structure includes a first gate insulation layer, a first barrier layer, a first work function material layer formed above the first barrier layer, a second barrier layer formed above the first work function material layer, and a first conductive material formed above the second barrier layer. A second transistor device has a second threshold voltage different than the first threshold voltage and includes a second gate electrode structure positioned in a second cavity defined in the dielectric layer. The second gate electrode structure includes a second gate insulation layer, a second work function material layer, the second barrier layer formed above the second work function material layer, and a second conductive material formed above the second barrier layer.