公开(公告)号：US5654217A

公开(公告)日：1997-08-05

申请号：US413960

申请日：1995-03-30

申请人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

发明人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

IPC分类号： H01L21/8247 ,  H01L21/265

CPC分类号： H01L27/11526 ,  H01L27/11534 ,  H01L27/11543 ,  Y10S438/917 ,  Y10S438/947

摘要： Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

摘要翻译： 形成具有单个电池尺寸的快闪EEPROM单元阵列的技术被减少，从而增加可能形成在给定尺寸的半导体衬底上的电池数量。 在该过程的几个步骤中使用电介质间隔物控制正被蚀刻或注入离子的区域，使之比通过最高分辨率光刻可以获得的更小。 包括分离通道和非分离通道（无选择晶体管）类型的存储单元。 示例单元采用具有分离的浮置，控制和擦除栅极的三个多晶硅层。 形成具有较高导电性均匀性的存储单元栅极的技术包括沉积未掺杂的多晶硅，然后使用离子注入来引入掺杂剂。 通过CVD沉积和干蚀刻在该工艺的早期阶段形成场氧化物。 存储单元阵列和相邻的外围组件以协调的方式形成在单个集成电路芯片上。

公开(公告)号：US08546214B2

公开(公告)日：2013-10-01

申请号：US12887328

申请日：2010-09-21

申请人： Takashi Whitney Orimoto ,  Atsushi Suyama ,  Ming Tian ,  Henry Chin ,  Henry Chien ,  Vinod Robert Purayath ,  Dana Lee

发明人： Takashi Whitney Orimoto ,  Atsushi Suyama ,  Ming Tian ,  Henry Chin ,  Henry Chien ,  Vinod Robert Purayath ,  Dana Lee

IPC分类号： H01L21/8242

CPC分类号： H01L21/28291 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/788

摘要： Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.

摘要翻译： 公开了非电压存储和用于制造非易失性存储器的技术。 在一些实施例中，非易失性存储元件的控制栅极的至少一部分由p型多晶硅形成。 在一个实施例中，控制栅极的下部是p型多晶硅。 控制栅极的上部可以是p型多晶硅，n型多晶硅，金属，金属氮化物等。即使在高Vpgm下，控制栅中的P型多晶硅也可能不会消耗。 因此，如果控制门耗尽，可能会发生的一些问题得到缓解。 例如，具有至少部分p型多晶硅的控制栅极的存储单元可以用比由n型多晶硅形成的存储单元低的Vpgm来编程。

公开(公告)号：US20090259068A1

公开(公告)日：2009-10-15

申请号：US12365507

申请日：2009-02-04

申请人： Eric Haupfear ,  Jerald D. Heise ,  Amy L. Jorgenson ,  Michael Rogers ,  Henry Chien ,  Eduardo Casanova ,  William Hooper ,  William Scholle ,  Juan Arhancet ,  Mark A. Leiber ,  Kent Wittler ,  Karen A. Wittler

发明人： Eric Haupfear ,  Jerald D. Heise ,  Amy L. Jorgenson ,  Michael Rogers ,  Henry Chien ,  Eduardo Casanova ,  William Hooper ,  William Scholle ,  Juan Arhancet ,  Mark A. Leiber ,  Kent Wittler ,  Karen A. Wittler

IPC分类号： C07F9/38 ,  B01D1/00 ,  B01D9/00

CPC分类号： C07F9/3813 ,  Y02P20/582

摘要： This invention generally relates to liquid phase oxidation processes for making N-(phosphonomethyl)glycine (also known in the agricultural chemical industry as glyphosate) and related compounds. This invention, for example, particularly relates to processes wherein an N-(phosphonomethyl)iminodiacetic acid (NPMIDA) substrate (i.e., N-(phosphonomethyl)iminodiacetic acid, a salt of N-(phosphonomethyl)iminodiacetic acid, or an ester of N-(phosphonomethyl)iminodiacetic acid) is continuously oxidized to form an N-(phosphonomethyl)glycine product (i.e., N-(phosphonomethyl)glycine, a salt of N-(phosphonomethyl)glycine, or an ester of N-(phosphonomethyl)glycine). This invention also, for example, particularly relates to processes wherein an N-(phosphonomethyl)iminodiacetic acid substrate is oxidized to form an N-(phosphonomethyl)glycine product, which, in turn, is crystallized (at least in part) in an adiabatic crystallizer.

摘要翻译： 本发明一般涉及制备N-（膦酰基甲基）甘氨酸（农业化学工业中也称为草甘膦）和相关化合物的液相氧化方法。 本发明特别涉及N-（膦酰基甲基）亚氨基二乙酸（NPMIDA）底物（即N-（膦酰基甲基）亚氨基二乙酸，N-（膦酰基甲基）亚氨基二乙酸的盐或N - （膦酰基甲基）亚氨基二乙酸）连续氧化形成N-（膦酰基甲基）甘氨酸产物（即N-（膦酰基甲基）甘氨酸，N-（膦酰基甲基）甘氨酸的盐或N-（膦酰基甲基）甘氨酸的酯 ）。 本发明还特别涉及其中N-（膦酰基甲基）亚氨基二乙酸底物被氧化以形成N-（膦酰基甲基）甘氨酸产物的方法，其反过来在绝热中结晶（至少部分地） 结晶器。

公开(公告)号：US07252383B2

公开(公告)日：2007-08-07

申请号：US11014826

申请日：2004-12-20

申请人： Francis Ho ,  Henry Chien ,  Yu-Chin Li ,  Wen-Hung Hsu ,  Chung-Hua Tsai ,  Minglu Chen

发明人： Francis Ho ,  Henry Chien ,  Yu-Chin Li ,  Wen-Hung Hsu ,  Chung-Hua Tsai ,  Minglu Chen

IPC分类号： G03B31/00 ,  G03B21/14 ,  G03B21/22 ,  G03B21/26 ,  H04N5/64

CPC分类号： G03B21/14 ,  G03B21/54 ,  G03B31/00

摘要： The present invention discloses an improved wireless audio output assembly for projectors, which comprises a system unit having a projector circuit therein and a projector lens disposed on the exterior of the system unit, and the system unit has a card-type wireless audio output circuit installed therein and a wireless active speaker installed on the exterior of the system unit, so that a projector can be used as a standalone device without connecting to external cables to read data from a memory card, view video images, and read audio/video signals of an optical disk. The projector can be upgraded to the user's desired wireless audio output circuit by inserting various different cards for the expansion.

摘要翻译： 本发明公开了一种用于投影机的改进的无线音频输出组件，其包括其中具有投影仪电路的系统单元和设置在系统单元的外部的投影仪透镜，并且系统单元具有安装在卡式无线音频输出电路 其中安装在系统单元的外部的无线主动扬声器，使得投影仪可以用作独立设备而不连接到外部电缆以从存储卡读取数据，观看视频图像和读取音频/视频信号 光盘。 投影机可以通过插入各种不同的扩展卡来升级到用户所需的无线音频输出电路。

公开(公告)号：US06959991B2

公开(公告)日：2005-11-01

申请号：US10721328

申请日：2003-11-26

申请人： Francis Ho ,  Minglu Chen ,  Ray Chiu ,  Kevin Kao ,  Jin Fu Sun ,  Bear Tsai ,  Chao Kuan Wu ,  Jason Mar ,  David Li ,  Henry Chien ,  Johnson Yang ,  Alex Chung ,  Yu-Chin Li ,  Chang Te Yang

发明人： Francis Ho ,  Minglu Chen ,  Ray Chiu ,  Kevin Kao ,  Jin Fu Sun ,  Bear Tsai ,  Chao Kuan Wu ,  Jason Mar ,  David Li ,  Henry Chien ,  Johnson Yang ,  Alex Chung ,  Yu-Chin Li ,  Chang Te Yang

IPC分类号： H04N5/38 ,  H04N5/60 ,  H04N5/74 ,  H04N5/775 ,  G03B21/14

CPC分类号： H04N9/3141 ,  H04N5/38 ,  H04N5/60 ,  H04N5/74 ,  H04N5/775 ,  H04N21/4184 ,  H04N21/42646 ,  H04N21/43637 ,  H04N21/8106

摘要： An integrated projector comprising a body with a projector circuit internally and a projection lens externally, a card reader installed on the body to read the data inside the memory card, a video interface installed on the body to receive video signals, and a video player that is a DVD player built-in inside the body. Users can read the data in the memory card, watch TV and watch DVD with a single projector without extra wiring.

摘要翻译： 一种集成投影机，其包括内部具有投影仪电路的主体和外部的投影透镜，安装在身体上以读取存储卡内部的数据的读卡器，安装在身体上以接收视频信号的视频接口以及视频播放器， 是内置在身体内的DVD播放机。 用户可以使用单个投影机读取存储卡中的数据，观看电视和观看DVD，无需额外的接线。

公开(公告)号：US5756385A

公开(公告)日：1998-05-26

申请号：US562198

申请日：1995-11-22

申请人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

发明人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  H01L27/11534 ,  H01L27/11543 ,  Y10S438/981

摘要： Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

摘要翻译： 形成具有单个电池尺寸的快闪EEPROM单元阵列的技术被减少，从而增加可能形成在给定尺寸的半导体衬底上的电池数量。 在该过程的几个步骤中使用电介质间隔物将被离子注入或注入的区域控制在比通过最高分辨率光刻法获得的更小的区域。 包括分离通道和非分离通道（无选择晶体管）类型的存储单元。 示例单元采用具有分离的浮置，控制和擦除栅极的三个多晶硅层。 形成具有较高导电性均匀性的存储单元栅极的技术包括沉积未掺杂的多晶硅，然后使用离子注入来引入掺杂剂。 通过CVD沉积和干蚀刻在该工艺的早期阶段形成场氧化物。 存储单元阵列和相邻的外围组件以协调的方式形成在单个集成电路芯片上。

公开(公告)号：US5747359A

公开(公告)日：1998-05-05

申请号：US787852

申请日：1997-01-23

申请人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

发明人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

IPC分类号： H01L21/8247 ,  H01L21/465

CPC分类号： H01L27/11526 ,  H01L27/11534 ,  H01L27/11543 ,  Y10S438/917 ,  Y10S438/947

摘要： Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

摘要翻译： 形成具有单个电池尺寸的快闪EEPROM单元阵列的技术被减少，从而增加可能形成在给定尺寸的半导体衬底上的电池数量。 在该过程的几个步骤中使用电介质间隔物将被离子注入或注入的区域控制在比通过最高分辨率光刻法获得的更小的区域。 包括分离通道和非分离通道（无选择晶体管）类型的存储单元。 示例单元采用具有分离的浮置，控制和擦除栅极的三个多晶硅层。 形成具有较高导电性均匀性的存储单元栅极的技术包括沉积未掺杂的多晶硅，然后使用离子注入来引入掺杂剂。 通过CVD沉积和干蚀刻在该工艺的早期阶段形成场氧化物。 存储单元阵列和相邻的外围组件以协调的方式形成在单个集成电路芯片上。

公开(公告)号：US5534456A

公开(公告)日：1996-07-09

申请号：US414333

申请日：1995-03-30

申请人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

发明人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  H01L27/11534 ,  H01L27/11543 ,  Y10S438/917 ,  Y10S438/947

摘要： Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

摘要翻译： 形成具有单个电池尺寸的快闪EEPROM单元阵列的技术被减少，从而增加可能形成在给定尺寸的半导体衬底上的电池数量。 在该过程的几个步骤中使用电介质间隔物控制正被蚀刻或注入离子的区域，使之比通过最高分辨率光刻可以获得的更小。 包括分离通道和非分离通道（无选择晶体管）类型的存储单元。 示例单元采用具有分离的浮置，控制和擦除栅极的三个多晶硅层。 形成具有较高导电性均匀性的存储单元栅极的技术包括沉积未掺杂的多晶硅，然后使用离子注入来引入掺杂剂。 通过CVD沉积和干蚀刻在该工艺的早期阶段形成场氧化物。 存储单元阵列和相邻的外围组件以协调的方式形成在单个集成电路芯片上。

公开(公告)号：US20110260235A1

公开(公告)日：2011-10-27

申请号：US12887328

申请日：2010-09-21

申请人： Takashi Whitney Orimoto ,  Atsushi Suyama ,  Ming Tian ,  Henry Chin ,  Henry Chien ,  Vinod Robert Purayath ,  Dana Lee

发明人： Takashi Whitney Orimoto ,  Atsushi Suyama ,  Ming Tian ,  Henry Chin ,  Henry Chien ,  Vinod Robert Purayath ,  Dana Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28291 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/788

摘要： Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.

摘要翻译： 公开了非电压存储和用于制造非易失性存储器的技术。 在一些实施例中，非易失性存储元件的控制栅极的至少一部分由p型多晶硅形成。 在一个实施例中，控制栅极的下部是p型多晶硅。 控制栅极的上部可以是p型多晶硅，n型多晶硅，金属，金属氮化物等。即使在高Vpgm下，控制栅中的P型多晶硅也可能不会消耗。 因此，如果控制门耗尽，可能会发生的一些问题得到缓解。 例如，具有至少部分p型多晶硅的控制栅极的存储单元可以用比由n型多晶硅形成的存储单元低的Vpgm来编程。

公开(公告)号：US07504534B2

公开(公告)日：2009-03-17

申请号：US11285721

申请日：2005-11-22

申请人： Eric A. Haupfear ,  Henry Chien ,  Eduardo Casanova ,  William B. Hooper

发明人： Eric A. Haupfear ,  Henry Chien ,  Eduardo Casanova ,  William B. Hooper

IPC分类号： C07F9/22

CPC分类号： C07F9/3813 ,  Y02P20/582

摘要： This invention generally relates to liquid phase oxidation processes for making N-(phosphonomethyl)glycine (also known in the agricultural chemical industry as glyphosate) and related compounds. This invention, for example, particularly relates to processes wherein an N-(phosphonomethyl)iminodiacetic acid (NPMIDA) substrate (i.e., N-(phosphonomethyl)iminodiacetic acid, a salt of N-(phosphonomethyl)iminodiacetic acid, or an ester of N-(phosphonomethyl)iminodiacetic acid) is continuously oxidized to form an N-(phosphonomethyl)glycine product (i.e., N-(phosphonomethyl)glycine, a salt of N-(phosphonomethyl)glycine, or an ester of N-(phosphonomethyl)glycine). This invention also, for example, particularly relates to processes wherein an N-(phosphonomethyl)iminodiacetic acid substrate is oxidized to form an N-(phosphonomethyl)glycine product, which, in turn, is crystallized (at least in part) in an adiabatic crystallizer.

摘要翻译： 本发明一般涉及制备N-（膦酰基甲基）甘氨酸（农业化学工业中也称为草甘膦）和相关化合物的液相氧化方法。 本发明特别涉及N-（膦酰基甲基）亚氨基二乙酸（NPMIDA）底物（即N-（膦酰基甲基）亚氨基二乙酸，N-（膦酰基甲基）亚氨基二乙酸的盐或N - （膦酰基甲基）亚氨基二乙酸）连续氧化形成N-（膦酰基甲基）甘氨酸产物（即N-（膦酰基甲基）甘氨酸，N-（膦酰基甲基）甘氨酸的盐或N-（膦酰基甲基）甘氨酸的酯 ）。 本发明还特别涉及其中N-（膦酰基甲基）亚氨基二乙酸底物被氧化以形成N-（膦酰基甲基）甘氨酸产物的方法，其反过来在绝热中结晶（至少部分地） 结晶器。