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87 条记录 (耗时 0.027 秒)

    Structure and methods for process integration in vertical DRAM cell fabrication
    52.
    发明授权
    Structure and methods for process integration in vertical DRAM cell fabrication 有权
    垂直DRAM单元制造过程集成的结构和方法

    公开(公告)号：US06790739B2

    公开(公告)日：2004-09-14

    申请号：US10249997

    申请日：2003-05-27

    申请人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

    发明人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

    IPC分类号： H01L2120

    CPC分类号： H01L27/10894 ,  H01L21/76224 ,  H01L27/10861

    摘要： A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.

    摘要翻译： 公开了一种用于处理半导体存储器件的方法，所述存储器件包括阵列区域和其上的支撑区域。 在本发明的示例性实施例中，该方法包括从阵列区域去除在器件上形成的初始衬垫氮化物材料。 然而，支撑区域中的初始衬垫氮化物材料仍然保持。 然后在阵列区域内形成有源器件区域，其中保持在支撑区域中的初始衬垫氮化物有助于保护支撑区域免受在阵列区域内形成有源器件区域期间实现的湿蚀刻工艺。

    Integrated spacer for gate/source/drain isolation in a vertical array structure
    54.
    发明授权
    Integrated spacer for gate/source/drain isolation in a vertical array structure 有权
    用于垂直阵列结构中栅极/源极/漏极隔离的集成间隔物

    公开(公告)号：US06677205B2

    公开(公告)日：2004-01-13

    申请号：US09966644

    申请日：2001-09-28

    申请人： Jochen Beintner

    发明人： Jochen Beintner

    IPC分类号： H01L21336

    CPC分类号： H01L27/10876 ,  H01L21/823487 ,  H01L27/10864 ,  H01L27/10888 ,  H01L27/10891

    摘要： Alignment tolerance for a vertical gate transistor device can be relaxed because of a spacer formed adjacent the trench. The gate electrode is formed of two materials that have etch selectivity between them, such that the outer material can be etched a predetermined depth into the recess without etching the inner material, resulting in the formation of a divot at the top of the trench. The divot is filled with an insulating material so that if source drain contacts are misaligned, the spacer serves to insulate the gate electrode from the contacts.

    摘要翻译： 由于在沟槽附近形成间隔物，因此垂直栅极晶体管器件的对准公差可以被放宽。 栅电极由两种在其间具有蚀刻选择性的材料形成，使得外部材料可以在没有蚀刻内部材料的情况下蚀刻到凹部中的预定深度，导致在沟槽顶部形成凹陷。 该凹陷填充有绝缘材料，使得如果源极漏极接触不对准，则间隔件用于使栅电极与触点绝缘。

    Self-aligned buried strap process using doped HDP oxide
    55.
    发明授权
    Self-aligned buried strap process using doped HDP oxide 失效
    使用掺杂HDP氧化物的自对准掩埋工艺

    公开(公告)号：US06667504B1

    公开(公告)日：2003-12-23

    申请号：US10249228

    申请日：2003-03-24

    申请人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

    发明人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

    IPC分类号： H01L27108

    CPC分类号： H01L27/10867 ,  H01L27/10864 ,  H01L29/945

    摘要： The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

    摘要翻译： 本发明提供了一种沟槽存储结构，其包括具有沟槽的衬底，沟槽下部的电容器导体，与电容器导体相邻的沟槽中的导电节点带，电容器导体上方的沟槽顶部氧化物，以及导电 埋在衬底中的邻近沟槽顶部氧化物的衬底。 沟槽顶部氧化物包括导电带上方的掺杂沟槽顶部氧化物层和掺杂沟槽顶部氧化物层上方的未掺杂沟槽顶部氧化物层。

    Field effect transistor and method of fabrication
    56.
    发明授权
    Field effect transistor and method of fabrication 有权

    公开(公告)号：US06602745B2

    公开(公告)日：2003-08-05

    申请号：US10066206

    申请日：2002-01-31

    申请人： Peter Thwaite ,  Jochen Beintner

    发明人： Peter Thwaite ,  Jochen Beintner

    IPC分类号： H01L21338

    CPC分类号： H01L29/1033 ,  H01L21/76235

    摘要： An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.

    Self-aligned channel implantation
    58.
    发明授权
    Self-aligned channel implantation 失效
    自对准通道植入

    公开(公告)号：US06329271B1

    公开(公告)日：2001-12-11

    申请号：US09588244

    申请日：2000-06-06

    申请人： Hiroyuki Akatsu ,  Yujun Li ,  Jochen Beintner

    发明人： Hiroyuki Akatsu ,  Yujun Li ,  Jochen Beintner

    IPC分类号： H01L21425

    CPC分类号： H01L29/66583 ,  H01L21/823412 ,  H01L29/105

    摘要： A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.

    摘要翻译： 短沟道绝缘栅场效应晶体管在半导体本体内部具有与晶体管相同的导电类型的掩埋层，但具有较高的杂质浓度。 掩埋层在沟道区下方，并且基本上只延伸晶体管的漏极和源极区之间的距离。 形成器件的过程在栅极下方的区域提供高浓度，以抑制横向耗尽区域膨胀，同时保持垂直方向上的逐渐连接。

    Memory cell structure and fabrication
    59.
    发明授权
    Memory cell structure and fabrication 失效
    存储单元结构和制造

    公开(公告)号：US06265742B1

    公开(公告)日：2001-07-24

    申请号：US09317662

    申请日：1999-05-24

    申请人： Ulrike Gruening ,  Jochen Beintner ,  Hans-Oliver Joachim

    发明人： Ulrike Gruening ,  Jochen Beintner ,  Hans-Oliver Joachim

    IPC分类号： H01L27108

    CPC分类号： H01L27/10864 ,  H01L27/10841

    摘要： A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.

    摘要翻译： 通过首先形成由晶片的主体部分隔开的一对垂直沟槽，在硅晶片的单晶体部分中形成用于DRAM中的一对存储单元。 在每个沟槽的壁之上形成电介质层之后，沟槽各自填充有多晶硅。 通过一对凹陷形成和凹陷填充步骤，在每个沟槽的顶部形成有与中间体部分外延生长的硅区域。 使每个外延区域用作在沟槽的下多晶硅填充物中具有其漏极的单独晶体管​​的主体，并且其源于在两个外延区域之间的单晶体体中间。 每个沟槽的较低多晶硅填充物也用作每个电池的电容器的存储节点，其体积用作电容器的另一个板。