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106 条记录 (耗时 0.025 秒)

    Interface circuit having a plurality of thresholding circuits
    52.
    发明授权
    Interface circuit having a plurality of thresholding circuits 失效
    接口电路具有多个阈值电路

    公开(公告)号：US5661482A

    公开(公告)日：1997-08-26

    申请号：US536243

    申请日：1995-09-29

    申请人： Guoliang Shou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    发明人： Guoliang Shou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    IPC分类号： H03M1/34 ,  G06J1/00 ,  H03M1/74 ,  H03K19/0175 ,  H03K19/00

    CPC分类号： G06J1/00

    摘要： An interface circuit comprising a digital to analog converter which comprises a register for receiving and holding each bit of a digital signal, a capacitive coupling for integrating total bits held in the register with weighting, an inverted amplifier circuit for receiving an output of the capacitive coupling and for outputting an analog output voltage, and a feedback capacitance for connecting an outputs of the inverted amplifier circuit to an input of the inverted amplifier circuit, an analog signal line to which the analog output voltage is connected, and an analog to digital converter which comprises a plurality thresholding circuits with stepwise thresholds to which the analog signal line is commonly inputted, each the thresholding circuit receiving outputs of the thresholding circuits of higher threshold with weighting so that the thresholding circuits repeatedly change the outputs from high level to low level or from low level to high level.

    摘要翻译： 一种接口电路，包括数模转换器，其包括用于接收和保持数字信号的每一位的寄存器，用于将保持在寄存器中的总比特积分为加权的电容耦合，反相放大器电路，用于接收电容耦合的输出 并且用于输出模拟输出电压，以及用于将反相放大器电路的输出连接到反相放大器电路的输入的反馈电容，连接有模拟输出电压的模拟信号线以及模数转换器， 包括具有逐步阈值的多个阈值电路，模拟信号线被共同地输入到该阈值电路中，每个阈值电路通过加权接收具有较高阈值的阈值电路的输出，使得阈值电路将输出从高电平重复地改变为低电平或从 低级到高级。

    Sampling and holding circuit
    54.
    发明授权
    Sampling and holding circuit 失效
    取样保持电路

    公开(公告)号：US5606274A

    公开(公告)日：1997-02-25

    申请号：US512317

    申请日：1995-08-08

    申请人： Guoliang Shou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    发明人： Guoliang Shou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    IPC分类号： G11C27/02

    CPC分类号： G11C27/026 ,  G11C27/024

    摘要： An analog input voltage is inputted to a first sample and hold circuit and a second sample and hold circuit is connected to an output of the first sample and hold circuit. The output of the first and second sample and hold circuits are inputted to a multiplexer which alternatively outputs the output of first sample and hold circuit or the second sample and hold circuit. When one of the first and second sample and hold circuits is refreshed, the output of the other sample and hold circuit is selected to be outputted from the multiplexer.

    摘要翻译： 模拟输入电压被输入到第一采样保持电路，第二采样和保持电路连接到第一采样和保持电路的输出。 第一和第二采样和保持电路的输出被输入到多路复用器，该多路复用器交替地输出第一采样保持电路或第二采样和保持电路的输出。 当第一和第二取样和保持电路中的一个被刷新时，另一采样和保持电路的输出被选择为从多路复用器输出。

    Computational circuit
    56.
    发明授权
    Computational circuit 失效
    计算电路

    公开(公告)号：US5565809A

    公开(公告)日：1996-10-15

    申请号：US468421

    申请日：1995-06-06

    申请人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： G06G7/06 ,  G06G7/14 ,  G06J1/00 ,  G11C27/02 ,  G06F7/44 ,  G06G7/16

    CPC分类号： G11C27/026 ,  G06G7/06 ,  G06G7/14 ,  G06J1/00 ,  G11C27/024

    摘要： A computational circuit that includes a pair of operational amplifiers, wherein one of the amplifiers receives an analog input voltage. Switching circuits are provided to selectively connect the outputs of the operational amplifiers to a common node and to respective inputs thereof via feedback lines. Capacitors are provided at the common node. A digital signal actuates the switching circuits so that one switching circuit is opened when the other is closed.

    摘要翻译： 一种包括一对运算放大器的计算电路，其中一个放大器接收模拟输入电压。 提供开关电路以通过反馈线将运算放大器的输出选择性地连接到公共节点及其相应的输入。 公共节点提供电容。 数字信号驱动开关电路，使得一个开关电路在另一个闭合时断开。

    Memory device
    57.
    发明授权
    Memory device 失效
    内存设备

    公开(公告)号：US5537348A

    公开(公告)日：1996-07-16

    申请号：US396618

    申请日：1995-03-01

    申请人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： G11C11/402 ,  G11C11/411 ,  G11C11/40

    CPC分类号： G11C11/4113

    摘要： A memory device that does not need to be refreshed and that has a relatively small size. The memory device includes a memory cell having a first PNP transistor, wherein an input voltage is provided to its base and its emitter is ground and a second NPN transistor having its base connected to the collector of the first transistor and its emitter connected to a power source, and wherein the collector of the second transistor is connected to the base of the first transistor.

    摘要翻译： 不需要刷新并且具有相对较小尺寸的存储器件。 存储器件包括具有第一PNP晶体管的存储单元，其中输入电压被提供到其基极并且其发射极被接地;以及第二NPN晶体管，其基极连接到第一晶体管的集电极，其发射极连接到功率 源极，并且其中第二晶体管的集电极连接到第一晶体管的基极。

    Memory device
    58.
    发明授权
    Memory device 失效
    内存设备

    公开(公告)号：US5477483A

    公开(公告)日：1995-12-19

    申请号：US100176

    申请日：1993-08-02

    申请人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Guoliang Shou ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： G11C11/402 ,  G11C11/411 ,  G11C11/40

    CPC分类号： G11C11/4113

    摘要： The present invention has an object to provide a memory device without the necessity of refreshment, whose circuit is small size.A memory device structuring a memory cell by connecting the follows: i) the first transistor of PNP type, having connection of input voltage to its base and grounding an emitter; ii) the second transistor of NPN type having connection of base to a collector of the first transistor, grounding collector and connection of power source to an emitter; and iii) the collector of the second transistor to the base of the first transistor.

    摘要翻译： 本发明的目的是提供一种不需要刷新的存储器件，其电路尺寸小。 通过连接以下结构来构造存储器单元的存储器件：i）PNP型的第一晶体管，其具有与其基极的输入电压的连接并使发射极接地; ii）具有基极与第一晶体管的集电极，接地集电极和电源连接到发射极的NPN型的第二晶体管; 和iii）第二晶体管的集电极到第一晶体管的基极。

    Weighted summing circuit
    59.
    发明授权
    Weighted summing circuit 失效
    加权求和电路

    公开(公告)号：US5465064A

    公开(公告)日：1995-11-07

    申请号：US190926

    申请日：1994-02-03

    申请人： Guoliang Shou ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Guoliang Shou ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： G06G7/14 ,  H03K12/00

    CPC分类号： G06G7/14

    摘要： A weighted summing circuit for minimizing bias voltage influence includes capacitive coupling and a closed loop inverter. The weighted summing circuit inputs the output of a capacitive coupling CP.sub.1 to serially connected first and second inverters INV.sub.1 and INV.sub.2, and includes grounded weighted capacitances C.sub.32 and C.sub.11, capacitance C.sub.21 connecting the first and the second inverters INV.sub.1 and INV.sub.2, and a capacitive coupling CP.sub.1 such that the closed loop gains of the first and second inverters INV.sub.1 and INV.sub.2 are substantially equal. The closed loop gains of the first and second inverters INV.sub.1 and INV.sub.2 are balanced.

    摘要翻译： 用于最小化偏置电压影响的加权求和电路包括电容耦合和闭环逆变器。 加权求和电路将电容耦合CP1的输出输入到串联的第一和第二反相器INV1和INV2，并且包括接地加权电容C32和C11，连接第一和第二反相器INV1和INV2的电容C21和电容耦合CP1 使得第一和第二反相器INV1和INV2的闭环增益基本相等。 第一和第二反相器INV1和INV2的闭环增益被平衡。

    Analog calculating
    60.
    发明授权
    Analog calculating 失效
    模拟计算

    公开(公告)号：US5416439A

    公开(公告)日：1995-05-16

    申请号：US174065

    申请日：1993-12-28

    申请人： Guoliang Shou ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Guoliang Shou ,  Weikang Yang ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： G06G7/16 ,  G06J1/00 ,  H03K17/00

    CPC分类号： G06J1/00

    摘要： An analog calculating circuit capable of storing data.A calculating circuit according to the present invention converts an analog voltage level to a time value by using a charging voltage of an RC circuit and stores the time value as a number of clock cycles in a digital counter. The circuit then converts another voltage level to a second time value and either adds the second time value to or subtracts it from the first time value. This yields a time value corresponding to a multiplication or division, respectively, of the analog voltage levels.

    摘要翻译： 一种能够存储数据的模拟计算电路。 根据本发明的计算电路通过使用RC电路的充电电压将模拟电压电平转换为时间值，并将时间值作为时钟周期数存储在数字计数器中。 然后，电路将另一电压电平转换为第二时间值，并将第二时间值与第一时间值相加或相减。 这产生分别对应于模拟电压电平的乘法或除法的时间值。