公开(公告)号：US11594273B2

公开(公告)日：2023-02-28

申请号：US17070865

申请日：2020-10-14

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Eric L. Pope ,  Melvin K. Benedict

IPC: G11C29/52 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4078

Abstract: Systems and methods for detecting a row hammer in a memory comprising a plurality of memory cells arranged in a plurality of rows may include: a plurality of detection cells in a subject row of memory cells, the detection cells to be set to respective initial states and configured to transition to a state different from their initial states in response to activations of memory cells in an adjacent row of memory cells; a comparison circuit to compare current states of the detection cells with initial states of the detection cells and to determine whether any of the detection cells have a current state that is different from their corresponding initial states; and a trigger circuit to trigger a refresh of the memory cells in the subject row based on a detection of detection cells in the subject row having current states that are different from their corresponding initial states.

公开(公告)号：US20220284944A1

公开(公告)日：2022-09-08

申请号：US17189897

申请日：2021-03-02

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Melvin K. Benedict ,  Eric L. Pope

IPC: G11C11/4078 ,  G11C11/403

Abstract: One embodiment provides a memory module. The memory module includes a plurality of rows of memory cells, with a respective row comprising one or more canary memory cells that are more susceptible to disturbance than non-canary memory cells, and a disturbance-detection circuit coupled to at least one canary memory cell of a corresponding row and configured to output a control signal in response to the disturbance to the canary memory cell exceeding a predetermined threshold.

公开(公告)号：US20200293671A1

公开(公告)日：2020-09-17

申请号：US16352293

申请日：2019-03-13

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Michael R. Krause ,  Melvin K. Benedict

IPC: G06F21/62 ,  G06F11/14 ,  G06F21/30 ,  G06F21/60 ,  H04L9/32

Abstract: A method as disclosed herein includes writing a data portion in a selected block of a primary medium. In some embodiments, the method includes determining a data authentication value for the selected block, identifying an emergency signal for the primary medium, and transferring the data portion and the data authentication value to a secondary medium when the emergency signal is asserted by a controller. In some embodiments, the method includes reading the data portion from the secondary medium, determining whether the data portion has been compromised in the secondary medium based on the data authentication value, and notifying a processor, with the controller, that the data portion has been compromised in the secondary medium.

公开(公告)号：US10740264B1

公开(公告)日：2020-08-11

申请号：US16397050

申请日：2019-04-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Melvin K. Benedict ,  Reza Bacchus ,  Mujeeb Rehman

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/42

Abstract: A synchronous differential memory interconnect may include a bidirectional differential data signal bus, a unidirectional differential command and address bus, and a differential clock signal. Memory read and write data may be transmitted over the data signal bus in a serial fashion.

公开(公告)号：US10468118B2

公开(公告)日：2019-11-05

申请号：US15115971

申请日：2014-03-03

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Andrew C. Walton ,  Melvin K. Benedict ,  Eric L. Pope ,  Erin A. Handgen

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/42 ,  G11C29/44 ,  G06F3/06 ,  G11C17/16 ,  G06F12/02 ,  G06F12/06 ,  G11C11/40 ,  G11C29/04

Abstract: Example implementations relate to dynamic random-access memory (DRAM) row sparing. In example implementations, utilization of a failed row of a DRAM device may be excluded. A fuse in the DRAM device may be blown to replace the failed row with a spare row. The fuse may be blown during runtime operation of the DRAM device. Error-correcting code (ECC) may be used to correct erroneous data from the failed row while the fuse is being blown. Accesses of the failed row may be redirected to the spare row after the fuse is blown.

公开(公告)号：US10373667B2

公开(公告)日：2019-08-06

申请号：US14913872

申请日：2013-08-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Melvin K. Benedict ,  Eric L. Pope

IPC: G06F3/00 ,  G11C11/406 ,  G06F12/10 ,  G06F11/07 ,  G06F3/06 ,  G06F13/16 ,  G11C7/02 ,  G06F21/56

Abstract: A technique includes determining that a row of memory has been activated at a threshold rate. Upon reaching the threshold rate, a refresh rate for the row of memory and an adjacent row of memory may be increased. Subsequent to the increase, the refresh rate may be returned to a default rate.

公开(公告)号：US20190171592A1

公开(公告)日：2019-06-06

申请号：US16258781

申请日：2019-01-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Melvin K. Benedict ,  Michael R. Krause ,  Mitchel E. Wright

IPC: G06F13/16 ,  G06F15/78

Abstract: A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.

公开(公告)号：US10261852B2

公开(公告)日：2019-04-16

申请号：US14894220

申请日：2013-05-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Melvin K. Benedict ,  Andrew C. Walton

IPC: G06F11/07 ,  G06F11/10 ,  G06F3/06

Abstract: A technique includes accessing error information generated in response to memory errors of a memory device. The error information generated in response to the memory errors of the memory device may then be determined as indicative of a row hammer error for the memory device.

公开(公告)号：US20170371809A1

公开(公告)日：2017-12-28

申请号：US15193146

申请日：2016-06-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Melvin K. Benedict

IPC: G06F12/14 ,  G06F11/07 ,  G06F12/1009 ,  G11C14/00

CPC classification number: G06F12/1408 ,  G06F12/1475 ,  G06F2212/1052 ,  G06F2212/402 ,  G11C7/24 ,  G11C2029/4402

Abstract: Encrypted memory access using page table attributes is disclosed. One example is a memory system including a memory controller at a memory interface. The memory controller includes an encryptor to control a plurality of memory access keys respectively associated with memory regions, where each memory region is allocated to a respective client, and an access manager to receive an access request from a client, the access request including a client access key to access a memory element. The access manager looks up a memory access key from a page table attribute associated with a physical address of the memory element, and determines if the access request is valid by comparing the client access key with the memory access key associated with the memory region that includes the memory element. Based on the determination and a mode of operation, the access manager provides a response to the access request.

公开(公告)号：US20170351455A1

公开(公告)日：2017-12-07

申请号：US15535828

申请日：2014-12-22

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Melvin K. Benedict ,  Lidia Warnes

IPC: G06F3/06 ,  G06F11/14

CPC classification number: G06F3/0619 ,  G06F1/30 ,  G06F11/1441 ,  G06F11/1469 ,  G06F11/3058 ,  G06F2201/84 ,  G06F2201/86

Abstract: Example implementations relate to generating statuses for data images. In example implementations, an event, in response to which a save operation is initiated on a memory module, may be identified. A data image may be generated during the save operation. A status may be generated for the generated data mage. The status may include an event portion indicative of the identified event, and a completion portion indicative of whether the save operation was completed.