公开(公告)号：US08652893B2

公开(公告)日：2014-02-18

申请号：US13510439

申请日：2011-11-25

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device and its manufacturing method, wherein the NMOS device is covered by a layer of silicon nitride film having a high ultraviolet light absorption coefficient through PECVD, said silicon nitride film can well absorb ultraviolet light when being subject to the stimulated laser surface anneal so as to achieve a good dehydrogenization effect, and after dehydrogenization, the silicon nitride film will have a high tensile stress; since the silicon nitride film has a high ultraviolet light absorption coefficient, there is no need to heat the substrate, thus avoiding the adverse influences to the device caused by heating the substrate to dehydrogenize, and maintaining the heat budget brought about by the PECVD process.

摘要翻译： 一种半导体器件及其制造方法，其中NMOS器件由通过PECVD具有高紫外光吸收系数的氮化硅膜覆盖，所述氮化硅膜在被受激光激光表面退火时可以很好地吸收紫外光，因此 为了达到良好的脱氢效果，脱氢后，氮化硅膜具有较高的拉伸应力; 由于氮化硅膜具有高的紫外光吸收系数，因此不需要加热基板，从而避免了由于将基板加热脱氢而导致的对器件的不利影响，并且保持了由PECVD工艺引起的热量预算。

公开(公告)号：US20140027857A1

公开(公告)日：2014-01-30

申请号：US13812498

申请日：2012-08-27

申请人： Huaxiang Yin ,  Jiang Yan ,  Dapeng Chen

发明人： Huaxiang Yin ,  Jiang Yan ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L29/66

CPC分类号： H01L27/088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7848

摘要： The present invention discloses a semiconductor device, comprising a substrate, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate stack structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, characterized in that each of the first gate stack structures comprises a first gate insulating layer, a first blocking layer, a first work function regulating layer and a resistance regulating layer, and each of the second gate stack structures comprises a second gate insulating layer, a first blocking layer, a second work function regulating layer, a first work function regulating layer and a resistance regulating layer.

摘要翻译： 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在两侧的衬底中的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极堆叠结构包括多个第一栅极叠层结构和多个第二栅极堆叠结构，其特征在于，每个第一栅极堆叠结构包括第一栅极绝缘层，第一阻挡层 ，第一功函数调节层和电阻调节层，并且每个第二栅极堆叠结构包括第二栅极绝缘层，第一阻挡层，第二功函数调节层，第一功函数调节层和电阻调节 层。

公开(公告)号：US20140017906A1

公开(公告)日：2014-01-16

申请号：US13695191

申请日：2012-07-26

申请人： Zuozhen Fu ,  Huaxiang Yin ,  Jiang Yan

发明人： Zuozhen Fu ,  Huaxiang Yin ,  Jiang Yan

IPC分类号： H01L21/02

CPC分类号： H01L21/02186 ,  C23C14/0641 ,  C23C14/18 ,  C23C14/34 ,  C23C14/54 ,  H01L21/2855

摘要： A method for forming titanium nitride by PVD is disclosed, comprising: generating ions of a noble gas by glow discharge under a vacuum condition that a nitrogen gas and the noble gas are supplied; nitriding a surface of a wafer and a surface of a titanium target with the nitrogen gas; bombarding the surface of the titanium target with the ions of the noble gas after they are accelerated in an electric field so that titanium ions and titanium nitride are sputtered; and forming a titanium nitride layer by depositing titanium nitride on the surface of the wafer in a magnetic field, while titanium ions are injected into the surface of the wafer so that stress is introduced into the titanium nitride layer, wherein non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased by increasing kinetic energy of titanium ions which are injected into the surface of the wafer. In the method for forming titanium nitride by PVD according to the present disclosure, kinetic energy of titanium ions which are injected into the surface of the wafer is increased by controlling process parameters so that non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased.

摘要翻译： 公开了一种通过PVD形成氮化钛的方法，包括：在供给氮气和惰性气体的真空条件下，通过辉光放电产生惰性气体的离子; 用氮气氮化晶片的表面和钛靶的表面; 在电场加速后，用惰性气体的离子轰击钛靶的表面，从而溅射钛离子和氮化钛; 以及通过在磁场中在晶片的表面上沉积氮化钛而形成氮化钛层，同时将钛离子注入晶片的表面，使得应力被引入到氮化钛层中，其中非晶化部分 通过提高注入到晶片表面的钛离子的动能来增加氮化钛层和氮化钛层中的应力。 在根据本公开的通过PVD形成氮化钛的方法中，通过控制工艺参数来增加注入晶片表面的钛离子的动能，使得氮化钛层的非结晶部分和应力在 氮化钛层增加。

公开(公告)号：US20130240996A1

公开(公告)日：2013-09-19

申请号：US13520611

申请日：2012-04-11

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833

摘要： The present invention discloses a semiconductor device, comprising a substrate, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer, the work function is close to the valence band (conduction band) edge; each of the second gate stack structures comprises a second gate insulating layer, a modified first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the second work function metal layer comprises implanted work function-regulating doped ions, which are simultaneously diffused to the first work function layer below to regulate the threshold such that the work function of the gate is close to the valence band (conduction band) edge and is opposite the original first work function, to thereby regulate the work function accurately.

摘要翻译： 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在两侧的衬底中的多个源极和漏极区域 所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层 ，第二功函数金属扩散阻挡层和栅极填充层，功函数接近价带（导带）边; 每个第二栅极堆叠结构包括第二栅极绝缘层，改性的第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，所述第二功函数金属层包括植入功函数调节 掺杂离子，其同时扩散到下面的第一功函数层以调节阈值，使得栅极的功函数接近价带（导带）边缘并与原始第一功函数相反，从而调节 工作功能准确。

公开(公告)号：US20130105906A1

公开(公告)日：2013-05-02

申请号：US13496477

申请日：2011-11-28

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842

摘要： The present invention relates to a CMOS device having dual metal gates and a method of manufacturing the same. The device comprising: a semiconductor substrate; a first-type MOS device comprising a first gate stack and a second-type MOS device comprising a second gate stack and having an opposite conductivity type, the first-type MOS device and the second-type MOS device being formed on the substrate; wherein the first gate stack is comprised of a first gate insulating layer, a first work function regulating layer formed on the first gate insulating layer and applicable to the first-type MOS device, and a first filling metal layer surrounded by the first work function regulating layer from the bottom and sides, and the second gate stack is comprised of a second gate insulating layer, a second work function regulating layer formed on the second gate insulating layer and applicable to the second-type MOS device, and a second filling metal layer surrounded by the second function regulating layer from the bottom and sides.

摘要翻译： 本发明涉及具有双金属栅极的CMOS器件及其制造方法。 该装置包括：半导体衬底; 包括第一栅极堆叠和第二类型MOS器件的第一型MOS器件，所述第一栅极堆叠和包括第二栅极堆叠并具有相反导电类型的第二类型MOS器件，所述第一类型MOS器件和所述第二类型MOS器件形成在所述衬底上; 其中所述第一栅极堆叠包括第一栅极绝缘层，形成在所述第一栅极绝缘层上并适用于所述第一类型MOS器件的第一功函数调节层，以及由所述第一功函数调节包围的第一填充金属层 并且第二栅极堆叠包括第二栅极绝缘层，形成在第二栅极绝缘层上并可应用于第二类型MOS器件的第二功函数调节层和第二填充金属层 由第二功能调节层从底部和侧面包围。

公开(公告)号：US20130005127A1

公开(公告)日：2013-01-03

申请号：US13322473

申请日：2011-07-27

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L21/283

CPC分类号： H01L29/66795

摘要： A method for manufacturing a multigate device is provided, comprising: providing a semiconductor substrate; etching the semiconductor substrate to form a protruding fin; etching the semiconductor substrate at the bottom of the fin so as to form a gap between the fin and the semiconductor substrate; forming a dielectric layer which covers the semiconductor substrate and the fin and fills the gap; and etching the dielectric layer so as to expose the top and a portion of sidewalls of the fin. The present invention can realize isolation between fins with a simple process, which costs relatively low and is suitable for massive industrial application.

摘要翻译： 提供了一种制造多栅装置的方法，包括：提供半导体衬底; 蚀刻半导体衬底以形成突出的鳍; 在鳍片的底部蚀刻半导体衬底，以在翅片和半导体衬底之间形成间隙; 形成覆盖所述半导体基板和所述翅片并填充所述间隙的电介质层; 并蚀刻该电介质层以暴露该翅片的顶部和一部分侧壁。 本发明可以通过简单的工艺实现翅片之间的隔离，成本相对较低，适合大规模的工业应用。

公开(公告)号：US08324061B2

公开(公告)日：2012-12-04

申请号：US13129419

申请日：2011-02-17

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76819 ,  H01L29/66545 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一栅极叠层，第一栅叠层在第一栅极导体和半导体衬底之间包括第一栅极导体和第一栅极电介质; 在半导体衬底上形成源/漏区; 在所述半导体衬底和所述第一栅极叠层上形成包括至少一个牺牲层和所述牺牲层下方的至少一个绝缘层的多层结构; 在所述多层结构上执行第一RIE; 在所述多层结构上执行第二RIE; 相对于绝缘层选择性地蚀刻第一栅极叠层，其中去除第一栅极导体并在绝缘层中形成开口; 以及在所述开口中形成第二栅极导体。

公开(公告)号：US20120139054A1

公开(公告)日：2012-06-07

申请号：US13108742

申请日：2011-05-16

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/28114 ,  H01L21/32137 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7845

摘要： The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device (200, 300), comprising a semiconductor substrate (202, 302); a channel formed on the semiconductor substrate (202, 302); a gate dielectric layer (204, 304) formed on the channel; a gate conductor (206, 306) formed on the gate dielectric layer (204, 304); and a source and a drain formed on both sides of the gate; wherein the gate conductor (206, 306) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel. In the present invention, the shape of the gate conductor may be adjusted by controlling the etching process parameter, thus the stress in the channel may be adjusted conveniently, meanwhile, it may be used in combination with other mechanisms that generate stresses to obtain the desired channel stress.

摘要翻译： 本发明涉及具有可调节通道应力的装置及其方法。 提供一种包括半导体衬底（202,302）的MOS器件（200,300）。 形成在半导体衬底（202,302）上的沟道; 形成在所述沟道上的栅介质层（204,304）; 形成在栅极介电层（204,304）上的栅极导体（206,306）; 以及形成在闸门两侧的源极和漏极; 其中所述栅极导体（206,306）具有用于产生要施加到所述沟道的第一应力的形状，以便调整所述沟道中的载流子的迁移率。 在本发明中，可以通过控制蚀刻工艺参数来调整栅极导体的形状，从而可以方便地调节通道中的应力，同时可以与产生应力的其他机构组合使用以获得期望的 通道压力。

公开(公告)号：US08022408B2

公开(公告)日：2011-09-20

申请号：US12659776

申请日：2010-03-22

申请人： Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-Young Kim ,  Huaxiang Yin ,  Xiaoxin Zhang

发明人： Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-Young Kim ,  Huaxiang Yin ,  Xiaoxin Zhang

IPC分类号： H01L29/04

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/814 ,  Y10S977/90 ,  Y10S977/932 ,  Y10S977/943

摘要： Example embodiments relate to a crystalline nanowire substrate having a structure in which a crystalline nanowire film having a relatively fine line-width may be formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the crystalline nanowire substrate may include preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.

摘要翻译： 示例性实施例涉及具有其中可以在基板上形成具有相对较细的线宽的结晶纳米线膜的结构的晶体纳米线基板及其制造方法，以及使用其制造薄膜晶体管的方法 。 制造结晶纳米线基板的方法可以包括制备基板，在基板上形成绝缘膜，在绝缘膜上形成硅膜，将绝缘膜和硅膜图案化成带状，减小线宽 绝缘膜通过底切蚀刻绝缘膜的至少一个侧面，并且通过使硅膜熔化和结晶而在绝缘膜的上表面上形成自对准硅纳米线膜。

公开(公告)号：US20110089998A1

公开(公告)日：2011-04-21

申请号：US12926475

申请日：2010-11-19

申请人： Huaxiang Yin ,  Youngsoo Park ,  Jaechul Park ,  Sunil Kim

发明人： Huaxiang Yin ,  Youngsoo Park ,  Jaechul Park ,  Sunil Kim

IPC分类号： G05F3/02

CPC分类号： H03K19/01714

摘要： An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first terminal is one of a first source and a first drain of the first transistor.