公开(公告)号：US20080079064A1

公开(公告)日：2008-04-03

申请号：US11898528

申请日：2007-09-13

申请人： Sheng-Chih Lai ,  Hang-Ting Lue

发明人： Sheng-Chih Lai ,  Hang-Ting Lue

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.

摘要翻译： 提供了具有非易失性存储器的半导体器件及其制造方法。 半导体器件包括基底材料和堆叠结构。 设置在基材上的堆叠结构至少包括隧穿层，捕获层和电介质层。 捕获层设置在隧道层上。 电介质层具有介电常数并且设置在捕获层上。 当电介质层进行处理时，电介质层从第一固态转变为第二固态。

公开(公告)号：US07315474B2

公开(公告)日：2008-01-01

申请号：US11324581

申请日：2006-01-03

申请人： Hang-Ting Lue

发明人： Hang-Ting Lue

IPC分类号： G11C11/34

CPC分类号： H01L29/792 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/265 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

摘要： Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays thereof and methods of operation.

摘要翻译： 存储单元包括：半导体衬底，其具有设置在衬底的表面下方并由沟道区分隔开的源极区和漏极区; 隧道电介质结构，其设置在所述沟道区上方，所述隧道介电结构包括至少一层具有小的空穴隧道势垒高度的层; 设置在隧道介电结构上方的电荷存储层; 设置在电荷存储层上方的绝缘层; 并且描述设置在绝缘层上方的栅极电极及其阵列和操作方法。

公开(公告)号：US20070258289A1

公开(公告)日：2007-11-08

申请号：US11381760

申请日：2006-05-05

申请人： Hang-Ting Lue

发明人： Hang-Ting Lue

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/0466 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427

摘要： A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state.

摘要翻译： 一种用于p沟道存储单元的编程方法，所述存储单元包括源极，漏极和栅极。 门施加第一电压，这导致Fowler-Nordheim（-FN）空穴注入，从而使存储器单元处于编程状态。

公开(公告)号：US20070037328A1

公开(公告)日：2007-02-15

申请号：US11203087

申请日：2005-08-15

申请人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

摘要翻译： 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

公开(公告)号：US20060205157A1

公开(公告)日：2006-09-14

申请号：US11429070

申请日：2006-05-05

申请人： Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

发明人： Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

摘要翻译： 提供非易失性存储器。 存储器包括衬底，电介质层，导电层，隔离层，掩埋位线，隧道电介质层，电荷俘获层，势垒介电层和字线。 其中介电层设置在基板上。 导电层设置在电介质层上。 隔离层设置在基板上并且邻近电介质层和导电层。 掩埋位线设置在衬底中并在隔离层下方。 隧道电介质层设置在导电层和隔离层的基板和侧壁上。 电荷捕获层设置在隧道介电层上，势垒介电层设置在电荷俘获层上。 字线设置在基板上，与埋入位线交叉。

公开(公告)号：US07067375B1

公开(公告)日：2006-06-27

申请号：US11018507

申请日：2004-12-20

申请人： Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

发明人： Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

公开(公告)号：US09082656B2

公开(公告)日：2015-07-14

申请号：US13294852

申请日：2011-11-11

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC分类号： H01L27/115

CPC分类号： H01L27/1157 ,  H01L27/11578

摘要： A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.

摘要翻译： 一种用于存储器阵列的制造方法包括首先在多个半导体条上形成多层电介质材料，然后在开关晶体管区域中暴露多层叠层。 在开关晶体管区域中暴露的多层堆叠被处理以形成不同于介电电荷俘获结构的栅介质结构。 然后形成字线和选择线。 介质电荷俘获存储器单元的3D阵列包括存储器单元的NAND串的堆叠。 多个开关晶体管耦合到NAND串，开关晶体管包括栅极电介质结构，其中栅极电介质结构不同于介电电荷俘获结构。

公开(公告)号：US08951862B2

公开(公告)日：2015-02-10

申请号：US13347331

申请日：2012-01-10

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC分类号： H01L21/336

CPC分类号： H01L27/11582 ,  H01L29/7926

摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.

摘要翻译： 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 诸如硅的导电线形成在堆叠的非易失性存储器结构之上。 字线沟槽分离出相邻的硅线。 由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。 字线是在字线沟中制作的。

公开(公告)号：US08861273B2

公开(公告)日：2014-10-14

申请号：US12427587

申请日：2009-04-21

申请人： Hang-Ting Lue

发明人： Hang-Ting Lue

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115 ,  H01L29/51

CPC分类号： H01L21/28282 ,  G11C16/0433 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

摘要： A 2T cell NOR architecture based on the use of BE-SONOS for embedded memory includes memory cells having respective access transistors having access gates and memory transistors having memory gates arranged in series between the corresponding bit lines and one of the plural reference lines. A memory transistor in a memory cell comprises a semiconductor body including a channel having a channel surface and a charge storing dielectric stack between the memory gate and the channel surface. The dielectric stack comprises a bandgap engineered, tunneling dielectric layer contacting one of the gate (for gate injection tunneling) and the channel surface (for channel injection tunneling). The dielectric stack of the memory cell also includes a charge trapping dielectric layer on the tunneling dielectric layer and a blocking dielectric layer.

摘要翻译： 基于对嵌入式存储器使用BE-SONOS的2T单元NOR架构包括具有存取晶体管的存储单元，存储晶体管具有存取栅极和存储晶体管，存储晶体管具有串联布置在相应的位线和多条参考线之一中的存储栅极。 存储单元中的存储晶体管包括半导体本体，其包括具有沟道表面的沟道和在存储器栅极和沟道表面之间的电荷存储电介质叠层。 电介质堆叠包括接触栅极（用于栅极注入隧道）和沟道表面之一（用于沟道注入隧道）的带隙工程化的隧道电介质层。 存储单元的电介质叠层还包括在隧道介电层上的电荷捕获电介质层和阻挡电介质层。

公开(公告)号：US08860124B2

公开(公告)日：2014-10-14

申请号：US12553758

申请日：2009-09-03

申请人： Hang-Ting Lue ,  Yi-Hsuan Hsiao

发明人： Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC分类号： H01L29/66 ,  H01L27/115 ,  H01L29/51 ,  H01L29/792 ,  G11C16/04

CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/513

摘要： A memory device includes a plurality of semiconductor lines, such as body-tied fins, on a substrate. The lines including buried-channel regions doped for depletion mode operation. A storage structure lies on the plurality of lines, including tunnel insulating layer on the channel regions of the fins, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer. A plurality of word lines overlie the storage structure and cross over the channel regions of the semiconductor lines, whereby memory cells lie at cross-points of the word lines and the semiconductor lines.

摘要翻译： 存储器件在衬底上包括多个半导体线，例如体结翅片。 这些线包括掺杂用于耗尽模式操作的掩埋沟道区。 存储结构位于多条线上，包括鳍状物的沟道区上的隧道绝缘层，隧道绝缘层上的电荷存储层，以及电荷存储层上的阻挡绝缘层。 多个字线覆盖在存储结构上并与半导体线的沟道区交叉，由此存储单元位于字线和半导体线的交叉点。