公开(公告)号：US6038661A

公开(公告)日：2000-03-14

申请号：US524712

申请日：1995-09-07

申请人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Shigezumi Matsui ,  Susumu Narita

发明人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Shigezumi Matsui ,  Susumu Narita

IPC分类号： G06F11/00 ,  G06F9/30 ,  G06F9/32 ,  G06F9/48 ,  G06F12/10

CPC分类号： G06F9/32 ,  G06F9/30101

摘要： A vector point of an exception handler related to TLB miss exception events is obtained by reading a vector base address of a register VBR one time, and by adding a vector offset (H'400) thereto. A vector point of an exception handler related to exception events other than the TLB miss exception events is obtained by adding a vector offset to a value (vector base address) of the register VBR, and an exception code which is an address offset obtained by reading a value of the register EXPEVT or INTEVT one time is added to the vector point that is obtained. Thus, the processing is branched to a required exception handler to execute the exception event processing related to exception events other than the TLB miss exception events.

摘要翻译： 通过读取寄存器VBR的向量基地址一次并通过向其中添加向量偏移（H'400）来获得与TLB未命中异常事件相关的异常处理程序的向量点。 通过向寄存器VBR的值（向量基地址）添加矢量偏移，以及通过读取得到的地址偏移的异常代码，获得与除了TLB未命中异常事件之外的异常事件相关的异常处理程序的向量点 寄存器EXPEVT或INTEVT的值一次被添加到所获得的向量点。 因此，处理被分支到所需的异常处理程序，以执行与除了TLB未命中异常事件之外的异常事件相关的异常事件处理。

公开(公告)号：US5860127A

公开(公告)日：1999-01-12

申请号：US653278

申请日：1996-05-24

申请人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

发明人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F12/08

CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  Y02B60/1225

摘要： A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

摘要翻译： 构成比较器，使得命中信号phi命中为高，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个虚构时，命中信号变低。 当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。 当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。 这种新颖的结构实现了高速缓存操作。 当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

公开(公告)号：US5848247A

公开(公告)日：1998-12-08

申请号：US524701

申请日：1995-09-07

申请人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

发明人： Shigezumi Matsui ,  Ikuya Kawasaki ,  Susumu Narita ,  Masato Nemoto

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F13/4068 ,  G06F12/06 ,  G06F13/385 ,  G06F13/4243 ,  G06F12/0292

摘要： A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and in parallel controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

摘要翻译： 一种包括总线状态控制器并用于个人计算机等的微处理器。 总线状态控制器包括诸如等待控制器的控制寄存器，并且并行控制各种半导体存储器（ROM，突发ROM，SRAM，PSRAM，DRAM和同步RAM）和PC卡（存储器和I / O卡）的接口。 总线状态控制器中还包括控制寄存器，用于控制设置同步DRAM的PC卡启动信号的时间。 微处理器的外部总线的地址空间被分成预定数量的半导体存储器和PC卡固定分配的区域。 微处理器还包括用于将内部准备的逻辑地址转换为物理地址的存储器管理单元。

公开(公告)号：US5394558A

公开(公告)日：1995-02-28

申请号：US266900

申请日：1994-07-01

申请人： Fumio Arakawa ,  Susumu Narita ,  Kunio Uchiyama

发明人： Fumio Arakawa ,  Susumu Narita ,  Kunio Uchiyama

IPC分类号： G06F9/38 ,  G06F9/22 ,  G06F9/28 ,  G06F9/30 ,  G06F9/318

CPC分类号： G06F9/30145 ,  G06F9/30192 ,  G06F9/3836 ,  G06F9/3857

摘要： A data processor in which, when two primitive instructions are decoded by instruction decoders, a microprogram ROM is not used under the control of a selector, and the two primitive instructions are executed in parallel by instruction execution units in accordance with the decoded outputs of the instruction decoders. When a high performance instruction is decoded by one of the instruction decoders, at a first step processing, one of the instruction execution units selects the output of the one instruction decoder to execute the instruction. At a second step processing, the one instruction execution unit selects a microinstruction of the microprogram ROM and executes the instruction. It is therefore unnecessary to use the microprogram ROM for the execution of a primitive instruction and a high performance instruction at the first step processing, thereby reducing the capacity, area and power consumption of the microprogram ROM.

摘要翻译： 一种数据处理器，其中当两个基本指令被指令解码器解码时，在选择器的控制下不使用微程序ROM，并且两个基本指令由指令执行单元根据 指令解码器 当一个指令解码器解码高性能指令时，在第一步处理中，一个指令执行单元选择一个指令译码器的输出来执行该指令。 在第二步处理中，一个指令执行单元选择微程序ROM的微指令并执行该指令。 因此，在第一步处理中，不需要使用微程序ROM来执行原语指令和高性能指令，从而降低微程序ROM的容量，面积和功耗。

公开(公告)号：US5251534A

公开(公告)日：1993-10-12

申请号：US875642

申请日：1992-04-29

申请人： Yoshitake Yonekubo ,  Hideshi Koiwai ,  Susumu Narita

发明人： Yoshitake Yonekubo ,  Hideshi Koiwai ,  Susumu Narita

IPC分类号： E02F9/20 ,  F15B13/042 ,  G05G9/04 ,  F01B31/12

CPC分类号： E02F9/2004 ,  F15B13/042 ,  F15B13/0424 ,  G05G9/04 ,  Y10T137/87064 ,  Y10T137/87072

摘要： An input apparatus capable of concurrently accommodating itself to any external signal from a different hydraulic control system or the like. The apparatus includes electrical load sensors each arranged on a push rod or block for detecting the amount of operation of a control lever to generate an electrical signal corresponding to the amount of operation of the control lever. Also, an input apparatus which is capable of concurrently responding to both a signal generated by itself and an external signal fed thereto is provided. The apparatus includes a pilot section for exerting force which permits a shuttle to be moved against coiled compression springs. The pilot section is fed with a signal from an external hydraulic control system.

摘要翻译： 一种能够同时容纳来自不同液压控制系统等的任何外部信号的输入装置。 该装置包括各自布置在推杆或块上的电负载传感器，用于检测控制杆的操作量以产生对应于控制杆的操作量的电信号。 此外，提供能够同时响应自身产生的信号和馈送到其的外部信号的输入装置。 该装置包括用于施加力的导向部分，其允许梭子绕线圈压缩弹簧移动。 引导部分输入来自外部液压控制系统的信号。