公开(公告)号：US6143605A

公开(公告)日：2000-11-07

申请号：US41863

申请日：1998-03-12

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L28/84

摘要： A method of making a capacitor over a contact. The method comprises the steps of: (a) depositing an oxide layer over said contact; (b) forming a dual damascene opening in said oxide layer over said contact; (c) depositing a layer of insitu doped polysilicon over said dual damascene opening and said oxide layer; (d) depositing a layer of undoped amorphous polysilicon over said layer of insitu doped polysilicon; (e) removing said layer of undoped amorphous polysilicon and said layer of insitu doped polysilicon that is outside of said dual damascene opening; (f) removing said oxide layer to leave a dual damascene structure comprising insitu doped polysilicon and undoped amorphous polysilicon; (g) forming hemispherical grain (HSG) polysilicon on the surface of said dual damascene structure; (h) forming a dielectric layer over said dual damascene structure; and (i) forming a top electrode over said dielectric layer.

摘要翻译： 在触点上制作电容器的方法。 该方法包括以下步骤：（a）在所述触点上沉积氧化物层; （b）在所述触点上形成所述氧化物层中的双镶嵌开口; （c）在所述双镶嵌开口和所述氧化物层上沉积一层原位掺杂多晶硅; （d）在所述本征掺杂多晶硅层上沉积未掺杂的非晶多晶硅层; （e）去除在所述双镶嵌开口之外的所述非掺杂非晶多晶硅层和所述本征掺杂多晶硅层; （f）去除所述氧化物层以留下包括原位掺杂多晶硅和未掺杂的非晶多晶硅的双镶嵌结构; （g）在所述双镶嵌结构的表面上形成半球形晶粒（HSG）多晶硅; （h）在所述双镶嵌结构上形成电介质层; 和（i）在所述介电层上形成顶部电极。

公开(公告)号：US6117748A

公开(公告)日：2000-09-12

申请号：US60771

申请日：1998-04-15

申请人： Chine-Gie Lou ,  Yeur-Luen Tu ,  Ko-Hsing Chang

发明人： Chine-Gie Lou ,  Yeur-Luen Tu ,  Ko-Hsing Chang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A thin silicon dioxide layer is formed on a substrate to act as a pad oxide layer. Subsequently, a Si.sub.3 N.sub.4 or BN layer is deposited on the pad oxide layer. An in situ doped polysilicon layer is deposited on the Si.sub.3 N.sub.4 or BN layer. A trench is formed in the substrate. An oxide liner is formed along the walls of the trench and on the surface of the in situ doped polysilicon layer. A CVD oxide layer is formed on the oxide liner and refilled into the trench. A two-step chemical mechanical polishing (CMP) removes the layers to the surface of the Si.sub.3 N.sub.4 or BN layer. The first step of the two-step CMP is an oxide slurry CMP that is stopped at about 100 to 500 angstroms from the in situ doped polysilicon layer. The second step of the two-step CMP is a poly slurry CMP that is controlled to stop at the surface of the Si.sub.3 N.sub.4 or BN layer.

摘要翻译： 在基板上形成薄的二氧化硅层，作为衬垫氧化物层。 随后，在衬垫氧化物层上沉积Si 3 N 4或BN层。 在Si 3 N 4或BN层上沉积原位掺杂多晶硅层。 在衬底中形成沟槽。 沿着沟槽的壁和原位掺杂的多晶硅层的表面上形成氧化物衬垫。 在氧化物衬垫上形成CVD氧化层，并重新填充到沟槽中。 两步化学机械抛光（CMP）去除层到Si3N4或BN层的表面。 两步CMP的第一步是从原位掺杂的多晶硅层停止在约100至500埃处的氧化物浆料CMP。 两步CMP的第二步是控制在Si3N4或BN层表面停止的聚浆料CMP。

公开(公告)号：US6093590A

公开(公告)日：2000-07-25

申请号：US395109

申请日：1999-09-14

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L21/31053 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66575 ,  H01L29/4966 ,  H01L29/66545

摘要： A method of fabricating a transistor. A first dielectric layer with a high dielectric constant is formed on a substrate. An oxide layer is formed on the first dielectric layer. A silicon nitride layer is formed on the oxide layer. The silicon nitride layer, the oxide layer, and the first dielectric layer are patterned to form a dummy gate structure. A spacer is formed on a sidewall of the dummy gate structure. The spacer and the dummy gate structure together form a dummy gate. An ion implantation step with the dummy gate serving as a mask and a thermal annealing step are performed to form a source region and a drain region on opposite sides of the dummy gate in the substrate. A second dielectric layer is formed next to the spacer. A top surface of the second dielectric layer is approximately level with a top surface of the dummy gate structure. The silicon nitride layer is removed. A nitridation process is performed to convert the oxide layer into a nitride layer. A metal barrier layer is formed over the substrate to cover the second dielectric layer, the spacer, and the nitride layer. A metal layer is formed on the metal barrier layer. A planarization process is performed to remove a portion of the metal layer and the metal barrier layer to form a metal gate. A top surface of the metal gate is level with a top surface of the second dielectric layer.

摘要翻译： 一种制造晶体管的方法。 在基板上形成具有高介电常数的第一介质层。 在第一电介质层上形成氧化物层。 在氧化物层上形成氮化硅层。 将氮化硅层，氧化物层和第一介电层图案化以形成虚拟栅极结构。 在虚拟栅极结构的侧壁上形成间隔物。 间隔物和虚拟栅极结构一起形成虚拟栅极。 执行具有伪栅极作为掩模和热退火步骤的离子注入步骤，以在衬底中的伪栅极的相对侧上形成源极区域和漏极区域。 在间隔物旁边形成第二电介质层。 第二电介质层的顶表面与虚拟栅结构的顶表面几乎相等。 去除氮化硅层。 进行氮化处理以将氧化物层转化为氮化物层。 在衬底上形成金属阻挡层以覆盖第二电介质层，间隔物和氮化物层。 在金属阻挡层上形成金属层。 执行平面化处理以去除金属层和金属阻挡层的一部分以形成金属栅极。 金属栅极的顶表面与第二电介质层的顶表面平齐。

公开(公告)号：US6090679A

公开(公告)日：2000-07-18

申请号：US201280

申请日：1998-11-30

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L21/02 ,  H01L21/20

CPC分类号： H01L28/91 ,  H01L28/84

摘要： A method for forming a bottom storage node of a crown-shaped DRAM capacitor on a substrate is disclosed. The method comprises the steps of: forming a first insulating layer onto said substrate; forming a barrier layer onto said first insulating layer; patterning and etching said first insulating layer and said barrier layer, and stopping at said substrate, to form a contact opening; forming an amorphous silicon plug into said contact opening; forming a second insulating layer onto said amorphous silicon plug and said barrier layer; patterning and etching said second insulating layer, stopping at said barrier layer, to form a trench above said amorphous silicon plug; forming a bottom amorphous silicon layer along the bottom and sidewalls of said trench; forming a middle amorphous silicon layer atop said bottom amorphous silicon layer; forming a top amorphous silicon layer atop said middle amorphous silicon layer, wherein said top amorphous silicon layer is undoped, and wherein said middle amorphous silicon layer and said bottom amorphous silicon layer have different dopant concentrations greater than zero; removing said second insulating layer; removing said barrier layer to expose a portion of said amorphous silicon plug; and forming a hemispherical grain (HSG) polysilicon layer on surfaces of said top amorphous silicon layer and said bottom amorphous silicon layer and on exposed portion of said amorphous silicon plug.

摘要翻译： 公开了一种在基板上形成冠状DRAM电容器的底部存储节点的方法。 该方法包括以下步骤：在所述衬底上形成第一绝缘层; 在所述第一绝缘层上形成阻挡层; 图案化和蚀刻所述第一绝缘层和所述阻挡层，并在所述基板上停止形成接触开口; 在所述接触开口中形成非晶硅塞; 在所述非晶硅塞和所述阻挡层上形成第二绝缘层; 图案化和蚀刻所述第二绝缘层，停止在所述阻挡层处，以在所述非晶硅插塞之上形成沟槽; 沿着所述沟槽的底部和侧壁形成底部非晶硅层; 在所述底部非晶硅层的顶部形成中间非晶硅层; 在所述中间非晶硅层顶部形成顶部非晶硅层，其中所述顶部非晶硅层未掺杂，并且其中所述中间非晶硅层和所述底部非晶硅层具有大于零的不同掺杂剂浓度; 去除所述第二绝缘层; 去除所述阻挡层以暴露所述非晶硅插塞的一部分; 以及在所述顶部非晶硅层和所述底部非晶硅层的表面上以及所述非晶硅插塞的暴露部分上形成半球形晶粒（HSG）多晶硅层。

公开(公告)号：US5916823A

公开(公告)日：1999-06-29

申请号：US170859

申请日：1998-10-13

申请人： Chine-Gie Lou ,  Yeur-Luen Tu

发明人： Chine-Gie Lou ,  Yeur-Luen Tu

IPC分类号： H01L21/768 ,  H01L21/32 ,  C25D11/04

CPC分类号： H01L21/76831 ,  H01L21/7681 ,  H01L21/76832

摘要： A method for forming a dual damascene structure on a substrate is disclosed. The method comprises the steps of: forming a liner oxide layer onto the substrate; forming a first low k dielectric layer atop the liner oxide layer; forming a cap oxide layer atop the first low k dielectric layer; forming a first nitride layer atop the cap oxide layer; patterning and etching the first nitride layer to form a contact opening; forming a second low k dielectric layer into the contact opening and atop the first nitride layer; forming a second nitride layer atop the second low k dielectric layer; forming a photoresist layer atop the second nitride layer; patterning and developing the photoresist layer to expose a trench opening, wherein the trench opening is of different dimension than the contact opening; forming a dual damascene opening by etching the second nitride layer and the second low k dielectric layer, using the photoresist layer as a mask, and by etching the cap oxide layer, the first low k dielectric layer and the liner oxide layer, using the first nitride layer as a mask; stripping the photoresist layer; forming oxide sidewall spacers into the dual damascene opening; and depositing a conductive layer into the dual damascene opening.

摘要翻译： 公开了一种在衬底上形成双镶嵌结构的方法。 该方法包括以下步骤：在衬底上形成衬垫氧化物层; 在衬垫氧化物层的上方形成第一低k电介质层; 在第一低k电介质层的顶部形成帽氧化物层; 在所述盖氧化物层顶上形成第一氮化物层; 图案化和蚀刻第一氮化物层以形成接触开口; 在所述接触开口中和所述第一氮化物层的顶上形成第二低k电介质层; 在所述第二低k电介质层的顶部形成第二氮化物层; 在所述第二氮化物层的顶部形成光致抗蚀剂层; 图案化和显影光致抗蚀剂层以露出沟槽开口，其中沟槽开口的尺寸与接触开口不同; 通过使用所述光致抗蚀剂层作为掩模蚀刻所述第二氮化物层和所述第二低k电介质层，并且通过使用所述第一低k介电层和所述衬底氧化物层蚀刻所述第一低k电介质层和所述衬里氧化物层来形成双镶嵌开口 氮化物层作为掩模; 剥离光致抗蚀剂层; 在所述双镶嵌开口中形成氧化物侧壁间隔物; 以及将导电层沉积到双镶嵌开口中。

公开(公告)号：US5827766A

公开(公告)日：1998-10-27

申请号：US988915

申请日：1997-12-11

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90

摘要： The present invention provides two main embodiments of a method of manufacturing a high capacitance cylindrical capacitor for a DRAM. The capacitor of the invention has a high capacitance because of the addition area 48C under the upper cylinder 48A and the hemispherical grain (HSG) layer 49 72. The first embodiment of the invention forms a HSG layer 49 over the inside of the cylindrical electrode 48A. The second embodiment forms a HSG layer 72 over both the inside and outside of the cylindrical electrode 70A. The invention also features four preferred methods for forming the first and second openings 30 34 in the second insulating layer. The first and second preferred methods use two optical masks to define the openings 30 34. The third and fourth methods use one photoresist layer 100 with 3 different thickness areas and a three step etch to define the first and second openings 30 34.

摘要翻译： 本发明提供了制造用于DRAM的高电容圆柱形电容器的方法的两个主要实施例。 本发明的电容器由于在上部圆筒48A和半球状晶粒（HSG）层49,72之下的添加区域48C具有高电容。本发明的第一实施例在圆柱形电极48A的内部形成HSG层49 。 第二实施例在圆柱形电极70A的内部和外部形成HSG层72。 本发明还具有在第二绝缘层中形成第一和第二开口30 34的四种优选方法。 第一和第二优选方法使用两个光学掩模来限定开口30 34.第三和第四方法使用具有3个不同厚度区域的一个光致抗蚀剂层100和三步蚀刻来限定第一和第二开口30 34。

公开(公告)号：US5618747A

公开(公告)日：1997-04-08

申请号：US657073

申请日：1996-06-03

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L28/84

摘要： A process, and apparatus, for depositing hemispherical grained polysilicon layers, used for the fabrication of stacked capacitor structures, for DRAM devices, has been developed. The hemispherical grained polysilicon layer is deposited in an LPCVD tool, equipped with multiple heating zones, to allow the narrow temperature range needed for maximum surface roughness of the hemispherical grained polysilicon layers, to be obtained. In addition the LPCVD tool features multiple reactant injection inlets, reducing reactant concentration depletion across the length of the reaction zone, thus improving the uniformity of the hemispherical grained layers, from wafer to wafer.

摘要翻译： 已经开发了用于沉积用于DRAM器件的层叠电容器结构的半球状粒状多晶硅层的工艺和装置。 将半球形多晶硅层沉积在配有多个加热区的LPCVD工具中，以获得半球状多晶硅层的最大表面粗糙度所需的窄温度范围。 此外，LPCVD工具具有多个反应物注入入口，减少了跨越反应区长度的反应物浓度耗尽，从而提高了半晶粒纹理层从晶片到晶片的均匀性。

公开(公告)号：US06908810B2

公开(公告)日：2005-06-21

申请号：US09924903

申请日：2001-08-08

申请人： Ling-Yen Yeh ,  Chine-Gie Lou

发明人： Ling-Yen Yeh ,  Chine-Gie Lou

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L21/8242

CPC分类号： H01L21/823481 ,  H01L21/76237

摘要： A method of preventing decreasing threshold voltage of a MOS transistor by formation of shallow trench isolation. Shallow trenches are formed to isolate first active regions and second active regions. The first active regions are located within a core circuit region, while the second active regions are located within a peripheral circuit region. A first ion implantation to form well regions is performed on the first and second active regions, respectively. A second ion implantation is performed on the second active region and edges of the first active regions to form second channel doping regions and to increase ion concentration at the edges of the first active regions, respectively. A third ion implantation is further performed on the first active regions to form first channel doping regions.

摘要翻译： 通过形成浅沟槽隔离来防止MOS晶体管的阈值电压降低的方法。 形成浅沟槽以隔离第一有源区和第二有源区。 第一有源区域位于核心电路区域内，而第二有源区域位于外围电路区域内。 在第一和第二活性区上分别进行形成阱区的第一离子注入。 在第二有源区域和第一有源区域的边缘上执行第二离子注入以形成第二沟道掺杂区域并分别增加第一有源区域的边缘处的离子浓度。 在第一有源区上进一步执行第三离子注入以形成第一沟道掺杂区。

公开(公告)号：US06403471B1

公开(公告)日：2002-06-11

申请号：US09429601

申请日：1999-10-28

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/76804 ,  H01L21/7681 ,  H01L21/76828

摘要： A dual damascene manufacturing process, which is applicable on a dual damascene structure, is described. The etching stop layer at a bottom of the trench line is removed followed by a thermal treatment to smooth out the surface at the bottom of the trench line and in the via to form a larger and smoother opening at the top part of the via. The via and the trench line are then filled with a barrier layer and a metal layer.

摘要翻译： 描述了适用于双镶嵌结构的双镶嵌制造工艺。 去除沟槽线底部的蚀刻停止层，然后进行热处理，以平滑沟槽线底部和通孔处的表面，以在通孔的顶部部分形成更大更平滑的开口。 然后，通孔和沟槽线填充有阻挡层和金属层。

公开(公告)号：US06376326B1

公开(公告)日：2002-04-23

申请号：US09675440

申请日：2000-09-28

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L2176

CPC分类号： H01L28/87 ,  H01L21/31616 ,  H01L28/55

摘要： A method of manufacturing a dynamic random access memory capacitor. To form the lower electrode of the capacitor involves using two different materials each having a different etching rate to form an alternately laid stack above a substrate. Differences in etching rates between the two materials are utilized to etch out a capacitor opening having serrated sidewalls. A polysilicon layer is next deposited into the capacitor opening. An aluminum layer and a titanium layer are sequentially formed over the polysilicon layer. An annealing operation is carried out in a nitrogen-filled atmosphere so that aluminum displaces polysilicon inside the capacitor opening. The silicon atoms in the polysilicon layer reacts with titanium atoms in the titanium layer to form a titanium silicide layer over the aluminum layer. The aluminum layer and the titanium silicide layer that cover the stacked layer are removed. The stacked layer is also removed to expose a fin-shaped aluminum lower electrode.

摘要翻译： 一种制造动态随机存取存储器电容器的方法。 为了形成电容器的下电极包括使用两种不同的材料，每种材料具有不同的蚀刻速率以在衬底上形成交替堆叠的叠层。 利用两种材料之间的蚀刻速率差异来蚀刻具有锯齿形侧壁的电容器开口。 随后将多晶硅层沉积到电容器开口中。 在多晶硅层上依次形成铝层和钛层。 在填充氮的气氛中进行退火操作，使得铝置换电容器开口内的多晶硅。 多晶硅层中的硅原子与钛层中的钛原子反应，在铝层上形成硅化钛层。 覆盖层叠层的铝层和硅化钛层被去除。 堆叠层也被去除以暴露鳍状铝下电极。