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133 条记录 (耗时 0.046 秒)

    Base pad polishing pad and multi-layer pad comprising the same
    51.
    发明授权
    Base pad polishing pad and multi-layer pad comprising the same 有权
    基座抛光垫和包括该基板的多层衬垫

    公开(公告)号：US07381121B2

    公开(公告)日：2008-06-03

    申请号：US10580617

    申请日：2005-02-16

    申请人： Eu-Gene Song ,  Ju-Yeol Lee ,  Sung-Min Kim ,  Jae-Seok Kim ,  Hyun-Woo Lee

    发明人： Eu-Gene Song ,  Ju-Yeol Lee ,  Sung-Min Kim ,  Jae-Seok Kim ,  Hyun-Woo Lee

    IPC分类号： B24D11/00

    CPC分类号： B24D11/02 ,  B24B37/22

    摘要： Disclosed is a base pad of polishing pad, which is used in conjunction with polishing slurry during a chemical-mechanical polishing or planarizing process, and a multilayer pad using the same. Since the base pad according to the present invention does not have fine pores, it is possible to prevent permeation of polishing slurry and water and to avoid non uniformity of physical properties. Thereby, it is possible to lengthen the lifetime of the polishing pad.

    摘要翻译： 公开了一种在化学机械抛光或平面化处理过程中与抛光浆料结合使用的抛光垫的基垫，以及使用其的多层垫。 由于根据本发明的基垫不具有细孔，因此可以防止研磨浆和水的渗透，并且可以避免物理性质的不均匀。 由此，可以延长抛光垫的寿命。

    Delay locked loop circuit in semiconductor device and its control method
    52.
    发明申请
    Delay locked loop circuit in semiconductor device and its control method 有权
    半导体器件中的延迟锁定环路及其控制方法

    公开(公告)号：US20080088349A1

    公开(公告)日：2008-04-17

    申请号：US11987935

    申请日：2007-12-06

    申请人： Hyun-Woo Lee

    发明人： Hyun-Woo Lee

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/095

    摘要： A delay locked loop (DLL) device includes a first and a second input buffers for receiving an external clock, a multiplexer for selectively outputting a first and a second internal clocks based on a most significant bit (MSB) signal, a delay means for delaying the first and the second internal clock which is selected by the multiplexer, a phase detector for comparing a phase of the first internal clock with that of a feedback clock which is feedbacked from the delay means to thereby output a comparing signal, a low pass filter (LPF) mode generator for outputting a locking signal, which checks a locking state of the feedback clock based on the comparing signal and a first and a second control signals, to the delay means, and a low pass filter for receiving the comparing signal to inform whether or not the comparing signal is erroneous to the delay means.

    摘要翻译： 延迟锁定环（DLL）装置包括用于接收外部时钟的第一和第二输入缓冲器，用于基于最高有效位（MSB）信号选择性地输出第一和第二内部时钟的多路复用器，用于延迟的延迟装置 由多路复用器选择的第一和第二内部时钟，相位检测器，用于将第一内部时钟的相位与从延迟装置反馈的反馈时钟的相位进行比较，从而输出比较信号;低通滤波器 （LPF）模式发生器，用于输出锁定信号，该锁定信号基于比较信号和第一和第二控制信号检测反馈时钟的锁定状态到延迟装置;以及低通滤波器，用于接收比较信号 通知比较信号是否对延迟装置是错误的。

    Delay locked loop
    53.
    发明授权
    Delay locked loop 失效
    延迟锁定环路

    公开(公告)号：US07282974B2

    公开(公告)日：2007-10-16

    申请号：US11323912

    申请日：2005-12-29

    申请人： Hyun-Woo Lee

    发明人： Hyun-Woo Lee

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/087

    摘要： A DLL for reducing jitter during a high frequency operation by separately controlling a coarse delay and a fine delay. The DLL includes a multiplexing unit for selectively outputting one of the rising clock and the falling clock; a first delay line for generating a first internal clock and a second internal clock; a second delay line for generating a first clock and a second clock; a delay line control unit for controlling the second delay line; a phase control unit for generating a first DLL clock and a second DLL clock by mixing the first clock and the second clock; and a phase comparing unit for comparing the first DLL clock and the second DLL clock with the rising clock to generate a lock signal for controlling an operation timing of the first delay line and the second delay line.

    摘要翻译： 用于通过分别控制粗略延迟和精细延迟来在高频操作期间减少抖动的DLL。 DLL包括用于选择性地输出上升时钟和下降时钟之一的复用单元; 用于产生第一内部时钟和第二内部时钟的第一延迟线; 用于产生第一时钟和第二时钟的第二延迟线; 延迟线控制单元，用于控制第二延迟线; 相位控制单元，用于通过混合第一时钟和第二时钟来产生第一DLL时钟和第二DLL时钟; 以及相位比较单元，用于将第一DLL时钟和第二DLL时钟与上升时钟进行比较，以产生用于控制第一延迟线和第二延迟线的操作定时的锁定信号。

    Register controlled delay locked loop and its control method
    55.
    发明申请
    Register controlled delay locked loop and its control method 有权

    公开(公告)号：US20060001465A1

    公开(公告)日：2006-01-05

    申请号：US11020597

    申请日：2004-12-21

    申请人： Jong-Tae Kwak ,  Hyun-Woo Lee

    发明人： Jong-Tae Kwak ,  Hyun-Woo Lee

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0818

    摘要： A register controlled delay locked loop (DLL), including: a coarse delay line for generating a delayed input clock signal by delaying an external clock signal; a fine delay line unit for receiving the delayed input clock signal in order to generate a first fine delayed clock signal and a second fine delayed clock signal; a phase detector for comparing phases of the external clock signal and a feed-backed clock signal in order to generate a phase detection signal based on the comparison result; a phase mixer for generating a mixed clock signal by mixing phases of the first fine delayed clock signal and the second fine delayed clock signal based on a weight value; and a mixer controller for generating the weight value based on the phase detection signal.

    Apparatus and method for measuring propagation delay in an NB-TDD CDMA mobile communication system
    56.
    发明授权
    Apparatus and method for measuring propagation delay in an NB-TDD CDMA mobile communication system 有权
    用于测量NB-TDD CDMA移动通信系统中的传播延迟的装置和方法

    公开(公告)号：US06956829B2

    公开(公告)日：2005-10-18

    申请号：US09989233

    申请日：2001-11-19

    申请人： Hyun-Woo Lee ,  Sung-Ho Choi ,  Kook-Heui Lee ,  Byung-Jae Kwak ,  Do-Young Kim ,  Sung-Oh Hwang

    发明人： Hyun-Woo Lee ,  Sung-Ho Choi ,  Kook-Heui Lee ,  Byung-Jae Kwak ,  Do-Young Kim ,  Sung-Oh Hwang

    IPC分类号： H04B17/00 ,  G01S13/74 ,  H04B7/26 ,  H04J3/00 ,  H04J13/00 ,  H04W24/08 ,  H04W52/04 ,  H04W64/00 ,  H04Q7/38

    CPC分类号： H04W56/001 ,  H04B7/2618 ,  H04B7/2668 ,  H04B7/2681 ,  H04W56/0045 ,  H04W56/0065 ,  H04W92/10

    摘要： Disclosed is a method for measuring a propagation delay value of a frame transmitted by a UE (User Equipment) to a Node B in a TDD (Time Division Duplexing) mobile communication system. The UE acquires synchronization with the Node B based on a downlink pilot channel signal transmitted in a period of a downlink pilot time slot, and determines an estimated round trip delay value T1 by comparing transmission power of a physical common channel signal in a first time slot with reception power of the same signal. The UE receives a transmission point correcting value T2 through a forward physical access channel (FPACH) signal transmitted from the Node B in a period of one downlink time slot among the time slots, and transmits a physical random access channel (PRACH) message with the estimated round trip delay value T1 at a transmission point determined based on T2 and T1.

    摘要翻译： 公开了一种用于在TDD（时分双工）移动通信系统中测量UE（用户设备）向节点B发送的帧的传播延迟值的方法。 UE基于在下行链路导频时隙的周期中发送的下行链路导频信道获取与节点B的同步，并且通过在第一时间内比较物理公共信道信号的发送功率来确定估计的往返延迟值T 1 时隙具有相同信号的接收功率。 UE通过在时隙中的一个下行链路时隙的周期内从节点B发送的前向物理接入信道（FPACH）信号接收发送点校正值T 2，并且发送具有 在基于T 2和T 1确定的传输点处的估计往返延迟值T 1。

    Internal clock signal generator and operating method thereof
    60.
    发明授权
    Internal clock signal generator and operating method thereof 有权
    内部时钟信号发生器及其操作方法

    公开(公告)号：US08471613B2

    公开(公告)日：2013-06-25

    申请号：US12648674

    申请日：2009-12-29

    申请人： Yong-Hoon Kim ,  Hyun-Woo Lee

    发明人： Yong-Hoon Kim ,  Hyun-Woo Lee

    IPC分类号： H03L7/06

    CPC分类号： H03L7/07 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0995

    摘要： An internal clock signal generation circuit is capable of controlling a unit delay time depending on a frequency of an external clock signal. The internal clock signal generation circuit includes an internal clock signal generation unit configured to generate an internal clock signal corresponding to a plurality of unit delay cells enabled in response to a control signal, and a unit delay time control unit configured to detect a frequency of an external clock signal and control a unit delay time of each of the plurality of unit delay cells.

    摘要翻译： 内部时钟信号发生电路能够根据外部时钟信号的频率来控制单位延迟时间。 内部时钟信号发生电路包括：内部时钟信号生成单元，被配置为产生与响应于控制信号而使能的多个单位延迟单元相对应的内部时钟信号;以及单位延迟时间控制单元， 外部时钟信号并且控制多个单元延迟单元中的每一个的单位延迟时间。