公开(公告)号：US20230187368A1

公开(公告)日：2023-06-15

申请号：US17548628

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L23/13 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L23/13 ,  H01L23/5383 ,  H01L23/5385 ,  H01L21/4857

Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a first substrate including a first surface, an opposing second surface and a recess opening extending through the first surface. The electronic assembly may also include a power delivery mold frame including a first mold surface, an opposing second mold surface, a plurality of first metal planes and a plurality of second metal planes extending between the first and second mold surfaces, the power delivery mold frame arranged in the recess opening and coupled to the first substrate through the first mold surface. The electronic assembly may further include a second substrate including a subsequent first surface, an opposing subsequent second surface, the second substrate coupled to the power delivery mold frame through a plurality of first solder bumps and further coupled to the first substrate through a plurality of second solder bumps at the subsequent first surface.

公开(公告)号：US20230065380A1

公开(公告)日：2023-03-02

申请号：US17411062

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00

Abstract: The present disclosure is directed to multichip semiconductor packages, and methods for making them, which includes a package substrate with an integrated bridge frame having a first horizontal portion positioned on a top surface of the package substrate, with first and second dies positioned overlapping the first horizontal portion of the bridge frame, and a second horizontal portion positioned on the bottom surface of the package substrate, with third and fourth dies positioned overlapping the second horizontal portion of the bridge frame. The bridge frame further includes first and second vertical portions separated by a portion of the package substrate positioned under the first horizontal portion of the bridge frame between the top surface and bottom surfaces of the package substrate, and a plurality of vertical interconnects adjacent to the first and second vertical portions of the bridge frame.

公开(公告)号：US20220078913A1

公开(公告)日：2022-03-10

申请号：US17090949

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Ranjul BALAKRISHNAN

IPC: H05K1/16

Abstract: For circuit boards that may be used in computing devices, a horizontal inductor, or an array of such inductors, may be coupled to a circuit board having a plurality of signal routing lines in a second layer from a surface of the circuit board and the horizontal inductor is positioned over these signal routing lines and may generate magnetic field lines that directionally follow the signal routing lines. The horizontal inductor may have a coiled wire with a central axis that is oriented horizontally with the surface of the circuit board. The horizontal inductor, or an array of such inductors, may be coupled to a support board attached to the circuit board.

公开(公告)号：US20220077070A1

公开(公告)日：2022-03-10

申请号：US17090933

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Choong Kooi CHEE ,  Bok Eng CHEAH ,  Teong Guan YEW ,  Jackson Chung Peng KONG ,  Loke Yip FOO

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/13 ,  H01L21/56 ,  H01L21/48

Abstract: According to various examples, a device is described. The device may include a package substrate. The device may also include a plurality of semiconductor devices disposed on the package substrate, wherein the plurality of semiconductor devices comprises top surfaces and bottom surfaces. The device may also include a plurality of interconnects coupled to the package substrate, wherein the plurality of interconnects are adjacent to the plurality of semiconductor devices. The device may also include a flyover bridge coupled to the top surfaces of the plurality of semiconductor devices and the plurality of interconnects, wherein the flyover bridge is directly coupled to the package substrate by the plurality of interconnects, and wherein the bottom surfaces of the plurality of semiconductor devices are electrically isolated from the package substrate.

公开(公告)号：US20220071022A1

公开(公告)日：2022-03-03

申请号：US17089748

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Seok Ling LIM

IPC: H05K3/34 ,  H05K1/18

Abstract: According to various examples, a device is described. The device may include a printed circuit board. The device may also include a first recess in the printed circuit board, wherein the first recess comprises a circular side surface and a bottom surface. The device may also include a first solder ball disposed in the first recess. The device may also include a first conductive wall positioned behind the circular side surface of the first recess, wherein the first conductive wall surrounds a side surface of the first solder ball.

公开(公告)号：US20220068846A1

公开(公告)日：2022-03-03

申请号：US17087667

申请日：2020-11-03

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Seok Ling LIM ,  Kooi Chi OOI

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01G4/224 ,  H01L23/00 ,  H01L25/18

Abstract: The present disclosure relates to a semiconductor package, that may include a package substrate, a base die arranged on and electrically coupled to the package substrate, and at least one power plane module arranged on the package substrate at a periphery of the base die. The power plane module may include a top surface and a bottom surface, and at least one vertical interleaving metal layer electrically coupled at the bottom surface to the package substrate. The semiconductor package may further include a semiconductor device including a first section disposed on the base die, and a second section disposed on the power plane module, wherein the second section of the semiconductor device may be electrically coupled to the at least one vertical interleaving metal layer at the top surface of the power plane module.

公开(公告)号：US20210384116A1

公开(公告)日：2021-12-09

申请号：US16987409

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Jackson Chung Peng KONG

IPC: H01L23/50 ,  H01L23/367 ,  H01L25/10 ,  H01L25/00 ,  H01R12/75

Abstract: A semiconductor package may include a semiconductor device coupled to a package substrate. The semiconductor package may also include an integrated heat spreader coupled to the package substrate. The semiconductor package may further include a package connector mounted on the integrated heat spreader. According to various examples, a semiconductor system is also described. The semiconductor system may include a first semiconductor package. The first semiconductor package may include a first package connector, and a first integrated heat spreader. The first package connector may be mounted on the first integrated heat spreader. The semiconductor system may also include a second semiconductor package. The second semiconductor package may include a second package connector, and a second integrated heat spreader. The second package connector may be mounted on the second integrated heat spreader. The first package connector may be electrically connected to the second package connector.

公开(公告)号：US20190013303A1

公开(公告)日：2019-01-10

申请号：US15996302

申请日：2018-06-01

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Min Suet LIM ,  Khang Choong YONG ,  Howe Yin LOO

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/00 ,  H01L21/50 ,  H01L49/02

Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having a stiffener that extends beyond a package substrate outer edge, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a package substrate having a first side, a second side opposite the first side, and an outer edge extending between the first side and the second side; an IC die coupled with the first side of the package substrate, where the IC die includes a power terminal; a stiffener coupled with the first side of the package substrate, where the stiffener surrounds the IC die and includes a conductive routing region coupled with the IC die power terminal, and a passive electronic device coupled with the conductive routing region. Other embodiments may be described and/or claimed.

公开(公告)号：US20180366423A1

公开(公告)日：2018-12-20

申请号：US15977617

申请日：2018-05-11

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Seok Ling LIM

IPC: H01L23/64 ,  H01L23/538 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L23/645 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19106

Abstract: Embodiments of the present disclosure provide a semiconductor package configured to provide for a disposition of one or more package components on a substrate within a footprint of a package die. In embodiments, the package may include a package substrate having a first side and a second side opposite the first side. An area of the first side of the package substrate within which a die is to be disposed may form a footprint of the die on the substrate. The package may further include a voltage reference plane coupled with the second side of the package substrate. At least a portion of the voltage reference plane may be disposed within the die footprint, to provide a reference voltage to components to be disposed within the footprint on the second side of the substrate, and to shield these components from electromagnetic interference. Other embodiments may be described and/or claimed.

公开(公告)号：US20180348823A1

公开(公告)日：2018-12-06

申请号：US15778383

申请日：2015-12-10

Applicant: INTEL CORPORATION

Inventor： Jackson Chung Peng KONG ,  Kooi Chi OOI ,  Bok Eng CHEAH ,  Eng Huat GOH

IPC: G06F1/16 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K3/28

CPC classification number: G06F1/1652 ,  G06F1/163

Abstract: A flexible electronic device that includes a flexible substrate having an upper surface and a lower surface and interconnects extending between the upper surface and the lower surface; a flexible display mounted directly to the upper surface of the flexible substrate such that the flexible display is electrically connected to the flexible substrate; a first encapsulant mounted to the upper surface of the flexible substrate such that the flexible display is at least partially embedded within the first encapsulant; an electronic component mounted to a lower surface of the flexible substrate such that the electronic component is electrically connected to the flexible substrate; a second encapsulant mounted to the lower surface of the flexible substrate such that the electronic component is at least partially embedded within the second encapsulant; a flexible casing that surrounds the electronic component and the second encapsulant.