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    VERTICAL INTERCONNECT DESIGN FOR IMPROVED ELECTRICAL PERFORMANCE
    5.
    发明申请
    VERTICAL INTERCONNECT DESIGN FOR IMPROVED ELECTRICAL PERFORMANCE 有权

    公开(公告)号：US20230113084A1

    公开(公告)日：2023-04-13

    申请号：US17498001

    申请日：2021-10-11

    Applicant: Intel Corporation

    Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Kok Hou TEH ,  Kooi Chi OOI ,  Li Wern CHEW

    IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00

    Abstract: The present disclosure generally relates to a printed circuit board assembly that may include a circuit board having a first surface and an opposing second surface. The printed circuit board assembly may also include a first interconnect barrel disposed in the circuit board. The first interconnect barrel may have a first length extending between the first surface and the second surface. The first interconnect barrel may include a first section, and may further include a second section spaced apart from the first section by a first gap having a first depth extending partially through the first length. The printed circuit board assembly may further include a first conductive trace coupled to the first section and a second conductive trace coupled to the second section at a first terminal.

    MULTI-CHIP PACKAGE WITH RECESSED MEMORY
    6.
    发明申请
    MULTI-CHIP PACKAGE WITH RECESSED MEMORY 有权

    公开(公告)号：US20220406753A1

    公开(公告)日：2022-12-22

    申请号：US17348802

    申请日：2021-06-16

    Applicant: Intel Corporation

    Inventor： Bok Eng CHEAH ,  Yang Liang POH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/13 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

    Abstract: The present disclosure is directed to semiconductor packages, and methods for making them, which includes a substrate with a top surface and a bottom surface, a substrate recess in the bottom surface of the substrate, a first device positioned over the top surface of the substrate, which has the first device at least partially overlapping the substrate recess, a mold material in the substrate recess, which has the mold material overlapping the bottom surface of the substrate adjacent to the substrate recess, a second device positioned in the substrate recess, and a plurality of interconnect vias in the substrate, which has at least one of the plurality interconnect vias coupled to the first and second devices to provide a direct signal connection therebetween that minimizes signal latency.

    MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
    7.
    发明申请
    MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING 有权

    公开(公告)号：US20220157694A1

    公开(公告)日：2022-05-19

    申请号：US17587647

    申请日：2022-01-28

    Applicant: Intel Corporation

    Inventor： Bok Eng CHEAH ,  Choong Kooi CHEE ,  Jackson Chung Peng KONG ,  Wai Ling LEE ,  Tat Hin TAN

    IPC: H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822

    Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

    SEMICONDUCTOR PACKAGE HAVING AN IMPEDANCE-BOOSTING CHANNEL
    9.
    发明申请
    SEMICONDUCTOR PACKAGE HAVING AN IMPEDANCE-BOOSTING CHANNEL 审中-公开

    公开(公告)号：US20190181080A1

    公开(公告)日：2019-06-13

    申请号：US16326688

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Khang Choong YONG ,  Po Yin YAW ,  Kok Hou TEH

    IPC: H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H01L25/10

    Abstract: Semiconductor package assemblies and semiconductor packages incorporating an impedance-boosting channel between a transmitter die and a receiver die are described. In an example, a semiconductor package includes a package substrate incorporating the impedance-boosting channel having a first arc segment connected to the transmitter die and a second arc segment connected to the receiver die. The arc segments extend around respective vertical axes passing through a transmitter die electrical bump and a receiver die electrical bump, respectively. Accordingly, the arc segments introduce an inductive circuitry to increase signal integrity of an electrical signal sent from the transmitter die to the receiver die.

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