公开(公告)号：US20240008177A1

公开(公告)日：2024-01-04

申请号：US17857055

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Kok Hou TEH

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/40

CPC classification number: H05K1/112 ,  H05K1/0296 ,  H05K3/4038 ,  H05K2201/09545

Abstract: The present disclosure is directed to a printed circuit board having a first surface and providing a signal pathway using a plurality of plated through hole (PTH) vias including a first set of PTH vias having a first PTH via coupled to a second PTH via and a first vertical separator being configured therebetween, with the first vertical separator extending a first depth from the first surface, and a second set of PTH vias having a third PTH via coupled to a fourth PTH via and a second vertical separator being configured therebetween, with the second vertical separator extending a second depth from the first surface, and a connector trace coupling the second PTH via to the third PTH via being positioned at a third depth from the first surface, for which the third depth is less than the first depth or the second depth.

公开(公告)号：US20240006341A1

公开(公告)日：2024-01-04

申请号：US17857059

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L25/18 ,  H01L24/16 ,  H01L21/4803 ,  H01L2224/16225

Abstract: A semiconductor package including: a package substrate including a base die disposed on a top surface of the package substrate, the base die including a plurality of electrical components disposed on a top surface of the base die, the plurality of electrical components including a first electrical component configured adjacent to a second electrical component, wherein the first electrical component and the second electrical component have an asymmetric form-factor; and a stiffener including: a stiffener main portion, wherein the stiffener main portion is affixed to the top surface of the package substrate and configured at least partially surrounding the base die; and a stiffener extension portion configured to extend from the stiffener main portion to be disposed at least partially over the top surface of the base die adjacent to the first electrical component and the second electrical component.

公开(公告)号：US20230120513A1

公开(公告)日：2023-04-20

申请号：US17971442

申请日：2022-10-21

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Seok Ling LIM ,  Kooi Chi OOI ,  Jenny Shio Yin ONG

IPC: H05K1/11

Abstract: Foldable Compression Attached Memory Modules (fCAMMs) and associated apparatus, assemblies and systems. The fCAMM comprises a compression contact module having a plurality of contact means arranged in one or more arrays on its underside, first and second fold modules including multiple memory devices, and flexible interconnects coupling the compression contact module to the first and second fold modules. Under one assembled configuration, portions of printed circuit boards (PCBs) for the first and second fold modules are folded over portions of the compression contact module. Under another configuration, the first fold module is disposed above the second fold module, which is disposed above the compression contact module. In an assembly or system including a motherboard, a compression mount technology (CMT) connector or a land grid array (LGA) assembly is disposed between the motherboard and the compression contact module. Bolster plates are used to urge the compression contact module toward the motherboard.

公开(公告)号：US20220077065A1

公开(公告)日：2022-03-10

申请号：US17089744

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Chin Lee KUAN ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/50 ,  H01L23/64 ,  H01L21/56 ,  H01L21/768

Abstract: A chip package including a chip; a substrate; an interposer module including a first layer having a larger surface area than the surface area of a second layer, wherein a bottom of the second layer is attached to a top of the first layer area creating an exposed surface area of the first layer; via openings extending at least partially through the first layer; via openings extending at least partially through the first layer and the second layer; a plurality of conductive routing electrically coupled between the via openings, wherein the chip is electrically coupled to the via openings of a top of the second layer, wherein the substrate is electrically coupled to via openings of a bottom of the first layer; and an electronic component electrically coupled to the via openings of the exposed surface area of the first layer.

公开(公告)号：US20220077060A1

公开(公告)日：2022-03-10

申请号：US17089745

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/50

Abstract: A semiconductor package including a molded power delivery module arranged between a package substrate and a semiconductor chip and including a plurality of input conductive structures and a plurality of reference conductive structures, wherein the input conductive structures alternate between the plurality of reference conductive structures, wherein the input conductive structure is electrically coupled with a chip input voltage terminal and a package input voltage terminal, wherein each of the plurality of reference conductive structures are electrically coupled with a semiconductor chip reference terminal and a package reference terminal.

公开(公告)号：US20220068833A1

公开(公告)日：2022-03-03

申请号：US17088618

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/495

Abstract: The present disclosure relates to a semiconductor package that may include a substrate, an interposer coupled to the substrate, a shield frame including at least one frame recess and at least one opening positioned over the interposer, a conductive shield layer on the shield frame, and a plurality of components coupled to the interposer.

公开(公告)号：US20210385948A1

公开(公告)日：2021-12-09

申请号：US17411064

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Tin Poay CHUAH ,  Jenny Shio Yin ONG ,  Seok Ling LIM

IPC: H05K1/11

Abstract: The present disclosure relates to a printed circuit board assembly including a first circuit board including a first footprint, the first circuit board further includes a plurality of first vertical vias extending between a first side and an opposing second side; a second circuit board including a second footprint smaller than the first footprint, the second circuit board further includes a plurality of second vertical vias extending between a subsequent first side and an opposing subsequent second side; an adhesive layer coupling the first side to the subsequent first side; and a plurality of third vertical vias extending through the first side and the subsequent first side.

公开(公告)号：US20190208620A1

公开(公告)日：2019-07-04

申请号：US16328535

申请日：2017-08-29

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Khang Choong YONG ,  Ramaswamy PARTHASARATHY

IPC: H05K1/02

CPC classification number: H05K1/0222 ,  H05K1/0219 ,  H05K1/0224 ,  H05K2201/0707 ,  H05K2201/09672

Abstract: Embodiments are generally directed to 3D high-inductive ground plane for crosstalk reduction. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer; a third layer below the second layer; and a three-dimensional (3D) ground plane, the 3D ground plane including a first plurality of segments on the third layer, a second plurality of segments on the second layer, and a plurality of metal vias to connect the first plurality of segments and the second plurality of segments in the ground plane.

公开(公告)号：US20190131257A1

公开(公告)日：2019-05-02

申请号：US16093828

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Khang Choong YONG ,  Howard Lincoln HECK

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498

Abstract: Semiconductor packages including a lateral interconnect having an arc segment to increase self-inductance of a signal line is described. In an example, the lateral interconnect includes a circular segment extending around an interconnect pad. The circular segment may extend around a vertical axis of a vertical interconnect to introduce an inductive circuitry to compensate for an impedance mismatch of the vertical interconnect.

公开(公告)号：US20250087542A1

公开(公告)日：2025-03-13

申请号：US18466019

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Man Chun OOH ,  Wei Chung LEE ,  Yean Ling SOON ,  Kor Oon LEE ,  Jackson Chung Peng KONG ,  Azniza ABD AZIZ ,  Piyush BHATT

IPC: H01L23/24 ,  H01L23/498

Abstract: The present disclosure is directed to an improved stiffener that has a body that has extension members positioned proximally to the corners of a semiconductor package substrate, and the extension members have bottom extension surfaces that extend beyond a periphery of a bottom surface of the semiconductor package substrate, and the bottom extension surfaces and the bottom surface of the semiconductor package substrate are co-planar. The present disclosure is also directed to a method for forming the improved stiffener with the extension members for a semiconductor package.