公开(公告)号：US12199623B2

公开(公告)日：2025-01-14

申请号：US17204792

申请日：2021-03-17

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Noam Familia

IPC: H03L7/099 ,  G06F1/10 ,  H03L7/07 ,  H03L7/081 ,  H03L7/093

Abstract: A digital phase spacing detector with programmable delay lines is described. Each programmable delay line receives a clock. The output of the programmable delay lines is compared by a logic and then passed through a glitch detector. Each of the clocks pass through the programmable delay lines that are tuned to a point where the clock edges at the output of the delay lines are aligned and glitches start appearing at the output of the logic. A calibration scheme uses replica cells (replica of VCO cells) in the measurement path. The calibration scheme calculates the average of clock phase differences through a digital control replica buffer, and this average clock phase difference is applied to the VCO delay stage cells. The PLL is then allowed to relock with the calibrated VCO delay stage cells. This process can be repeated several times to reduce the phase errors between the clock phases.

公开(公告)号：US20220070522A1

公开(公告)日：2022-03-03

申请号：US17523502

申请日：2021-11-10

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Nausheen Ansari ,  Howard Heck ,  Amit Kumar Srivastava

IPC: H04N21/43 ,  H04N21/422 ,  G06F13/38

Abstract: Embodiments relate to a controller subsystem that includes a virtual reality (VR) subsystem to: identify data received from a peripheral device as related to an audio/visual (A/V) function of the peripheral device; direct, based on the identification that the data is related to the A/V function of the peripheral device, the data to be stored in a memory subsystem of the controller subsystem; and facilitate transmission of an indication of a storage location of the data in the memory subsystem to a host system that is communicatively coupled with the controller subsystem. The controller subsystem further includes a graphics engine to: identify, in a message received from the host system based on the transmission of the indication of the storage location of the data, instructions related to rendering the data; and generate, based on the data received from the peripheral device, rendered data. Other embodiments may be described and claimed.

公开(公告)号：US20220004516A1

公开(公告)日：2022-01-06

申请号：US17479001

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42

Abstract: In one embodiment, an apparatus includes a host controller to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto a first line of the interconnect; a second driver to drive a clock signal onto a second line of the interconnect; and a mode control circuit to cause the second driver to drive the clock signal onto the second line of the interconnect in a first mode and to cause the first driver and the second driver to drive differential information onto the first line and the second line of the interconnect in a second mode. Other embodiments are described and claimed.

公开(公告)号：US20210218404A1

公开(公告)日：2021-07-15

申请号：US17196806

申请日：2021-03-09

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava

IPC: H03L7/087 ,  H03L7/23

Abstract: Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

公开(公告)号：US11030142B2

公开(公告)日：2021-06-08

申请号：US15635299

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Amit Kumar Srivastava ,  Nobuyuki Suzuki

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/364 ,  G06F13/24

Abstract: In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

公开(公告)号：US10979055B2

公开(公告)日：2021-04-13

申请号：US16780790

申请日：2020-02-03

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: H03L1/00 ,  H03K3/03 ,  H03L7/099

Abstract: An apparatus is provided which comprises: a first ring oscillator comprising at least one aging tolerant circuitry; a second ring oscillator comprising a non-aging tolerant circuitry; a first counter coupled to the first ring oscillator, wherein the first counter is to count a frequency of the first ring oscillator; a second counter coupled to the second ring oscillator, wherein the second counter is to count a frequency of the second ring oscillator; and logic to compare the frequencies of the first and second ring oscillators, and to generate one or more controls to mitigate aging of one or more devices.

公开(公告)号：US10942880B2

公开(公告)日：2021-03-09

申请号：US16236471

申请日：2018-12-29

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Asad Azam

IPC: G06F13/40 ,  G06F13/16

Abstract: An integrated circuit for monitoring components of the integrated circuit, comprising: a resource monitoring circuit configured to: track activity factors for a plurality of components of the integrated circuit; evaluate the activity factors for each of the plurality of components; determine whether an activity factor for a particular component of the plurality of components exceeds a threshold; and transmit, from the resource monitoring circuit, a signal to a software element, causing the software element to deactivate the particular component and activate an alternate component, when the activity factor for the particular component exceeds the threshold and the alternate component is available to substitute for the particular component.

公开(公告)号：US10938200B2

公开(公告)日：2021-03-02

申请号：US15443161

申请日：2017-02-27

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava ,  Karthik Ns ,  Raghavendra Devappa Sharma ,  Dharmaray Nedalgi ,  Prasad Bhilawadi

IPC: G06K19/00 ,  H02H3/18 ,  G06F1/26 ,  G06F1/3212 ,  H04B1/38 ,  H04L25/02

Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.

公开(公告)号：US20200379530A1

公开(公告)日：2020-12-03

申请号：US16943155

申请日：2020-07-30

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Rao Jagannadha Rapeta ,  Asad Azam

IPC: G06F1/20 ,  G05B15/02

Abstract: The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.

公开(公告)号：US10769084B2

公开(公告)日：2020-09-08

申请号：US15474117

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Duane G. Quiet ,  Amit Kumar Srivastava

IPC: G06F13/24 ,  G06F13/42

Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.