公开(公告)号：US20230132749A1

公开(公告)日：2023-05-04

申请号：US17517065

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Marko Radosavljevic ,  Cheng-Ying Huang ,  Willy Rachmady ,  Gilbert Dewey ,  Ashish Agrawal

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092

Abstract: Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. In an example, an upper (e.g., n-channel) device and a lower (e.g., p-channel) device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where the upper device is located vertically above the lower device. According to some embodiments, an internal spacer structure extends between the nanoribbons of the upper device and the nanoribbons of the lower device along the vertical direction, where the spacer structure has a stepwise or an otherwise outwardly protruding profile as it extends between the nanoribbons of the upper device and the lower device. Accordingly, in one example, a gate structure formed around the nanoribbons of both the n-channel device and the p-channel device exhibits a greater width in the region between the nanoribbons of the n-channel device and the nanoribbons of the p-channel device.

公开(公告)号：US11328988B2

公开(公告)日：2022-05-10

申请号：US16728887

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L27/12 ,  H01L23/522 ,  H01L21/768 ,  H01L21/762

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US11322620B2

公开(公告)日：2022-05-03

申请号：US16648974

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Van H. Le ,  Ashish Agrawal ,  Seung Hoon Sung ,  Abhishek A. Sharma ,  Ravi Pillarisetty

IPC: H01L29/786 ,  C30B29/08 ,  C30B29/40 ,  H01L27/088

Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

公开(公告)号：US11233148B2

公开(公告)日：2022-01-25

申请号：US16649304

申请日：2017-11-06

Applicant: INTEL CORPORATION

Inventor： Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Harold W. Kennel ,  Dipanjan Basu ,  Ashish Agrawal ,  Glenn A. Glass ,  Tahir Ghani ,  Anand S. Murthy

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US11164785B2

公开(公告)日：2021-11-02

申请号：US16728903

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Willy Rachmady ,  Anand Murthy ,  Ryan Keech ,  Cory Bomberger

IPC: H01L21/822 ,  H01L27/12 ,  H01L29/08 ,  H01L23/522 ,  H01L29/417 ,  H01L21/8238

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include monocrystalline source and drain material epitaxially grown from a monocrystalline channel material at a temperature low enough to avoid degradation of a lower level transistor structure and/or degradation of one or more low-k dielectric materials between the transistor levels. A highly conductive n-type silicon source and drain material may be selectively deposited at low temperatures with a high pressure CVD process. Multiple crystals of source drain material arranged in a vertically stacked multi-channel transistor structure may be contacted by a single contact metallization.

公开(公告)号：US11152290B2

公开(公告)日：2021-10-19

申请号：US16094817

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Van H. Le ,  Willy Rachmady ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L23/498 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

Abstract: A subfin layer is deposited on a substrate. A fin layer is deposited on the subfin layer. The subfin layer has a conduction band energy offset relative to the fin layer to prevent a leakage in the subfin layer. In one embodiment, the subfin layer comprises a group IV semiconductor material layer that has a bandgap greater than a bandgap of the fin layer.

公开(公告)号：US11018075B2

公开(公告)日：2021-05-25

申请号：US16221815

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L27/12 ,  H01L23/40 ,  H01L21/822 ,  H01L23/532 ,  H01L21/70

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

公开(公告)号：US10985263B2

公开(公告)日：2021-04-20

申请号：US16465763

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Dipanjan Basu ,  Ashish Agrawal ,  Van H. Le ,  Benjamin Chu-Kung ,  Harold W. Kennel ,  Glenn A. Glass ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200335610A1

公开(公告)日：2020-10-22

申请号：US16957667

申请日：2018-02-28

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US20200266296A1

公开(公告)日：2020-08-20

申请号：US16649304

申请日：2017-11-06

Applicant: INTEL CORPORATION

Inventor： Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Harold W. Kennel ,  Dipanjan Basu ,  Ashish Agrawal ,  Glenn A. Glass ,  Tahir Ghani ,  Anand S. Murthy

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.