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公开(公告)号：US11482614B2
公开(公告)日：2022-10-25
申请号：US16645962
申请日：2017-12-23
Applicant: Intel Corporation
Inventor： Ravi Pillarisetty , Willy Rachmady , Kanwaljit Singh , Nicole K. Thomas , Hubert C. George , Zachary R. Yoscovits , Roman Caudillo , Payam Amin , Jeanette M. Roberts , James S. Clarke
IPC: H01L29/66 , G06N10/00 , H01L27/088 , H01L29/12 , H01L29/165 , H01L29/423 , H01L29/43 , H01L29/82
Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.
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公开(公告)号：US11322591B2
公开(公告)日：2022-05-03
申请号：US16616427
申请日：2017-06-24
Applicant: Intel Corporation , Technische Universiteit Delft
IPC: H01L29/15 , G06N10/00 , H01L23/473 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/775
Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.
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公开(公告)号：US11158731B2
公开(公告)日：2021-10-26
申请号：US16642886
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Ravi Pillarisetty , Van H. Le , Nicole K. Thomas , Hubert C. George , Jeanette Roberts , Payam Amin , Zachary R. Yoscovits , Roman Caudillo , James S. Clarke , Roza Kotlyar , Kanwaljit Singh
IPC: H01L29/66 , G06N10/00 , H01L21/8234 , H01L27/088 , H01L27/12 , H01L29/15 , H01L29/78 , H01L29/82 , H01L29/43
Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.
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公开(公告)号：US20210280676A1
公开(公告)日：2021-09-09
申请号：US17321046
申请日：2021-05-14
Applicant: Intel Corporation , Technishce Universiteit Delft
Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.
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公开(公告)号：US11107908B2
公开(公告)日：2021-08-31
申请号：US16306540
申请日：2016-07-01
Applicant: Intel Corporation
Inventor： Sasikanth Manipatruni , Anurag Chaudhry , Dmitri E. Nikonov , Jasmeet S. Chawla , Christopher J. Wiegand , Kanwaljit Singh , Uygar E. Avci , Ian A. Young
IPC: H01L29/66 , H01L29/45 , H01L29/775 , H01L29/10 , H01L29/739 , H01L29/06 , B82Y10/00 , H01L29/786 , H01L29/423 , H01L29/417 , H01L21/285 , H01L29/16 , H01L29/20 , H01L29/24 , H01L29/47 , H01L29/78
Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.
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Patent Agency Ranking
公开(公告)号：US20200350423A1
公开(公告)日：2020-11-05
申请号：US16642886
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Ravi Pillarisetty , Van H. Le , Nicole K. Thomas , Hubert C. George , Jeanette Roberts , Payam Amin , Zachary R. Yoscovits , Roman Caudillo , James S. Clarke , Roza Kotlyar , Kanwaljit Singh
IPC: H01L29/66 , H01L29/82 , H01L29/78 , H01L27/088 , H01L27/12 , H01L21/8234 , H01L29/15 , G06N10/00
Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.
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公开(公告)号：US20200321436A1
公开(公告)日：2020-10-08
申请号：US16650299
申请日：2017-12-23
Applicant: Intel Corporation
Inventor： Ravi Pillarisetty , Hubert C. George , Nicole K. Thomas , Jeanette M. Roberts , Roman Caudillo , Zachary R. Yoscovits , Kanwaljit Singh , Roza Kotlyar , Patrick H. Keys , James S. Clarke
Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.
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公开(公告)号：US10475912B2
公开(公告)日：2019-11-12
申请号：US15900655
申请日：2018-02-20
Applicant: Intel Corporation
Inventor： Nicole K. Thomas , Ravi Pillarisetty , Kanwaljit Singh , Hubert C. George , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , Lester Lampert , James S. Clarke , Willy Rachmady
Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.
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公开(公告)号：US10388848B2
公开(公告)日：2019-08-20
申请号：US15924410
申请日：2018-03-19
Applicant: Intel Corporation
Inventor： Nicole K. Thomas , James S. Clarke , Jessica M. Torres , Lester Lampert , Ravi Pillarisetty , Hubert C. George , Kanwaljit Singh , Jeanette M. Roberts , Roman Caudillo , Zachary R. Yoscovits , David J. Michalak
Abstract: Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.
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公开(公告)号：US10347834B2
公开(公告)日：2019-07-09
申请号：US15928220
申请日：2018-03-22
Applicant: INTEL CORPORATION
Inventor： Nicole K. Thomas , Marko Radosavljevic , Sansaptak Dasgupta , Ravi Pillarisetty , Kanwaljit Singh , Hubert C. George , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , Lester Lampert , James S. Clarke
Abstract: Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.
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