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公开(公告)号：US20220058852A1
公开(公告)日：2022-02-24
申请号：US17497618
申请日：2021-10-08
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Arthur Hunter , Kamal Sinha , Scott Janus , Brent Insko , Vasanth Ranganathan , Lakshminarayanan Striramassarma
Abstract: Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.
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公开(公告)号：US20210258616A1
公开(公告)日：2021-08-19
申请号：US17111677
申请日：2020-12-04
Applicant: Intel Corporation
Inventor： Jill Boyce , Scott Janus , Itay Kaufman , Archie Sharma , Stanley Baran , Michael Apodaca , Prasoonkumar Surti , Srikanth Potluri , Barnan Das , Hugues Labbe , Jong Dae Oh , Gokcen Cilingir , Maria Bortman , Tzach Ashkenazi , Jonathan Distler , Atul Divekar , Mayuresh M. Varerkar , Narayan Biswal , Nilesh V. Shah , Atsuo Kuwahara , Kai Xiao , Jason Tanner , Jeffrey Tripp
Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.
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公开(公告)号：US11049266B2
公开(公告)日：2021-06-29
申请号：US16050468
申请日：2018-07-31
Applicant: Intel Corporation
Inventor： Scott Janus , Barnan Das , Hugues Labbe , Jong Dae Oh , Gokcen Cilingir , James Holland , Narayan Biswal , Yi-Jen Chiu , Qian Xu , Mayuresh Varerkar , Sang-Hee Lee , Stanley Baran , Srikanth Potluri , Jason Ross , Maruthi Sandeep Maddipatla
Abstract: An apparatus comprises a processor to divide a first point cloud data set frame representing a three dimensional space at a first point in time into a matrix of blocks, determine at least one three dimensional (3D) motion vector for at least a subset of blocks in the matrix of blocks, generate a predicted second point cloud data set frame representing a prediction of the three dimensional space at a second point in time by applying the at least one 3D motion vector to the subset of blocks in the matrix of blocks, compare the predicted second point cloud data set frame to a second point cloud data set frame representing a prediction of the three dimensional space at a second point in time to generate a prediction error parameter, and encode the second point cloud data set frame as a function of the first point cloud data set frame and the at least one three dimensional (3D) motion vector when the prediction error factor is beneath an error threshold to produce an encoded second point cloud data set frame.
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公开(公告)号：US11018863B2
公开(公告)日：2021-05-25
申请号：US16435083
申请日：2019-06-07
Applicant: Intel Corporation
Inventor： Balaji Vembu , Vidhya Krishnan , Sandeep S. Sodhi , Scott Janus , Daniel Nemiroff
Abstract: An embodiment of a graphics apparatus may include a graphics processor including a kernel executor, and a security engine communicatively coupled to the graphics processor. The security engine may be configured to create a kernel security key, encrypt an executable kernel for the kernel executor in accordance with the kernel security key, and share the kernel security key with the graphics processor.
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公开(公告)号：US20210035258A1
公开(公告)日：2021-02-04
申请号：US17064427
申请日：2020-10-06
Applicant: Intel Corporation
Inventor： Joydeep Ray , Scott Janus , Varghese George , Subramaniam Maiyuran , Altug Koker , Abhishek Appu , Prasoonkumar Surti , Vasanth Ranganathan , Andrei Valentin , Ashutosh Garg , Yoav Harel , Arthur Hunter, JR. , SungYe Kim , Mike Macpherson , Elmoustapha Ould-Ahmed-Vall , William Sadler , Lakshminarayanan Striramassarma , Vikranth Vemulapalli
Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.
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Patent Agency Ranking
公开(公告)号：US20200043182A1
公开(公告)日：2020-02-06
申请号：US16050468
申请日：2018-07-31
Applicant: Intel Corporation
Inventor： Scott Janus , Barnan Das , Hugues Labbe , Jong Dae Oh , Gokcen Cilingir , James Holland , Narayan Biswal , Yi-Jen Chiu , Qian Xu , Mayuresh Varerkar , Sang-Hee Lee , Stanley Baran , Srikanth Potluri , Jason Ross , Maruthi Sandeep Maddipatla
Abstract: Embodiments described herein provide an apparatus comprising a processor to divide a first point cloud data set frame representing a three dimensional space at a first point in time into a matrix of blocks, determine at least one three dimensional (3D) motion vector for at least a subset of blocks in the matrix of blocks, generate a predicted second point cloud data set frame representing a prediction of the three dimensional space at a second point in time by applying the at least one 3D motion vector to the subset of blocks in the matrix of blocks, compare the predicted second point cloud data set frame to a second point cloud data set frame representing a prediction of the three dimensional space at a second point in time to generate a prediction error parameter, and encode the second point cloud data set frame as a function of the first point cloud data set frame and the at least one three dimensional (3D) motion vector when the prediction error factor is beneath an error threshold to produce an encoded second point cloud data set frame. Other embodiments may be described and claimed.
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公开(公告)号：US10367639B2
公开(公告)日：2019-07-30
申请号：US15394324
申请日：2016-12-29
Applicant: Intel Corporation
Inventor： Balaji Vembu , Vidhya Krishnan , Sandeep S. Sodhi , Scott Janus , Daniel Nemiroff
Abstract: An embodiment of a graphics apparatus may include a graphics processor including a kernel executor, and a security engine communicatively coupled to the graphics processor. The security engine may be configured to create a kernel security key, encrypt an executable kernel for the kernel executor in accordance with the kernel security key, and share the kernel security key with the graphics processor.
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公开(公告)号：US20160162260A1
公开(公告)日：2016-06-09
申请号：US14928878
申请日：2015-10-30
Applicant: Intel Corporation
Inventor： Scott Janus
IPC: G06F3/16
CPC classification number: G06F3/167 , G06F3/048 , G06F3/1446 , G09G3/003 , H04R1/00 , H04S7/302 , H04S2400/11
Abstract: Techniques for improved audio localization for visual effects are described. In one embodiment, for example, an apparatus may comprise a processor circuit and an audio management module, and the audio management module may be operable by the processor circuit to determine a position of a user interface element in a presentation area, determine an audio effect corresponding to the user interface element, determine audio location information for the audio effect based on the position of the user interface element, the audio location information defining an apparent position for the audio effect, and generate audio playback information for the audio effect based on the audio location information. Other embodiments are described and claimed.
Abstract translation: 描述了用于改善视觉效果的音频定位的技术。 在一个实施例中，例如，设备可以包括处理器电路和音频管理模块，并且音频管理模块可以由处理器电路操作以确定用户界面元素在呈现区域中的位置，确定音频效果 对应于用户界面元素，基于用户界面元素的位置确定音频效果的音频位置信息，音频位置信息定义音频效果的明显位置，并且基于音频效果生成用于音频效果的音频回放信息 音频位置信息。 描述和要求保护其他实施例。
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59.发明申请公开(公告)号：US20250061172A1
公开(公告)日：2025-02-20
申请号：US18883195
申请日：2024-09-12
Applicant: Intel Corporation
Inventor： Anbang Yao , Ming Lu , Yikai Wang , Scott Janus , Sungye Kim
IPC: G06F18/2136 , G06T11/00
Abstract: Embodiments are generally directed to methods and apparatuses of spatially sparse convolution module for visual rendering and synthesis. An embodiment of a method for image processing, comprising: receiving an input image by a convolution layer of a neural network to generate a plurality of feature maps; performing spatially sparse convolution on the plurality of feature maps to generate spatially sparse feature maps; and upsampling the spatially sparse feature maps to generate an output image.
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公开(公告)号：US20250004981A1
公开(公告)日：2025-01-02
申请号：US18793247
申请日：2024-08-02
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Altug Koker , Aravindh Anantaraman , Elmoustapha Ould-Ahmed-Vall , Valentin Andrei , Nicolas Galoppo Von Borries , Varghese George , Mike Macpherson , Subramaniam Maiyuran , Joydeep Ray , Lakshminarayana Striramassarma , Scott Janus , Brent Insko , Vasanth Ranganathan , Kamal Sinha , Arthur Hunter , Prasoonkumar Surti , David Puffer , James Valerio , Ankur N. Shah
IPC: G06F15/78 , G06F7/544 , G06F7/575 , G06F7/58 , G06F9/30 , G06F9/38 , G06F9/50 , G06F12/02 , G06F12/06 , G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0862 , G06F12/0866 , G06F12/0871 , G06F12/0875 , G06F12/0882 , G06F12/0891 , G06F12/0893 , G06F12/0895 , G06F12/0897 , G06F12/1009 , G06F12/128 , G06F15/80 , G06F17/16 , G06F17/18 , G06N3/08 , G06T1/20 , G06T1/60 , G06T15/06 , H03M7/46
Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.
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