公开(公告)号：US11756150B2

公开(公告)日：2023-09-12

申请号：US17674781

申请日：2022-02-17

Applicant: Intel Corporation

Inventor： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

CPC classification number: G06T1/20 ,  G06F13/4027

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US20230051190A1

公开(公告)日：2023-02-16

申请号：US17865666

申请日：2022-07-15

Applicant: Intel Corporation

Inventor： Vikranth Vemulapalli ,  Lakshminarayanan Striramassarma ,  Mike MacPherson ,  Aravindh Anantaraman ,  Ben Ashbaugh ,  Murali Ramadoss ,  William B. Sadler ,  Jonathan Pearce ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter, JR. ,  Prasoonkumar Surti ,  Nicolas Galoppo von Borries ,  Joydeep Ray ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Altug Koker ,  Sungye Kim ,  Subramaniam Maiyuran ,  Valentin Andrei

IPC: G06F12/0862 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：US20220261347A1

公开(公告)日：2022-08-18

申请号：US17732308

申请日：2022-04-28

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Ben Ashbaugh ,  Jonathan Pearce ,  Abhishek Appu ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Elmoustapha Ould-Ahmed-Vall ,  Aravindh Anantaraman ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Yoav Harel ,  Arthur Hunter,, JR. ,  Brent Insko ,  Scott Janus ,  Pattabhiraman K ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Marian Alin Petre ,  Murali Ramadoss ,  Shailesh Shah ,  Kamal Sinha ,  Prasoonkumar Surti ,  Vikranth Vemulapalli

IPC: G06F12/0802 ,  G06F9/30

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：US11409693B2

公开(公告)日：2022-08-09

申请号：US17321885

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Aravindh Anantaraman ,  Abhishek R. Appu ,  Altug Koker ,  Elmoustapha Ould-Ahmed-Vall ,  Valentin Andrei ,  Subramaniam Maiyuran ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Mike MacPherson ,  Ben Ashbaugh ,  Murali Ramadoss ,  Vikranth Vemulapalli ,  William Sadler ,  Jonathan Pearce ,  Sungye Kim

IPC: G06T1/00 ,  G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220188967A1

公开(公告)日：2022-06-16

申请号：US17685117

申请日：2022-03-02

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Josh Mastronarde ,  Naveen Matam ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets, With such an interchangeable design, cache or DRAM memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

公开(公告)号：US20220179787A1

公开(公告)日：2022-06-09

申请号：US17428530

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Ben Ashbaugh ,  Jonathan Pearce ,  Abhishek Appu ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Elmoustapha Ould-Ahmed-Vall ,  Aravindh Anantaraman ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Yoav Harel ,  Arthur Hunter, Jr. ,  Brent Insko ,  Scott Janus ,  Pattabhiraman K ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Marian Alin Petre ,  Murali Ramadoss ,  Shailesh Shah ,  Kamal Sinha ,  Prasoonkumar Surti ,  Vikranth Vemulapalli

IPC: G06F12/0802 ,  G06F9/30

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：US20220156068A1

公开(公告)日：2022-05-19

申请号：US17530040

申请日：2021-11-18

Applicant: Intel Corporation

Inventor： Michael Cole ,  Alexandr Kurylev ,  Subramaniam Maiyuran ,  Vikranth Vemulapalli ,  Sriharsha Vadlamani ,  Piotr Reiter

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0815 ,  G06F9/50

Abstract: Systems and methods for minimally intrusive instruction pointer-aware processing resource activity profiling are disclosed. In one embodiment, a graphics processor includes a grouping of processing resources and control logic that is associated with the grouping of processing resources. The control logic is configured to sample a state of at least one processing resource of the grouping of processing resources and to determine activity data from the state with the activity data including at least one of stalls and reason counts for stalling activity, instruction types, pipeline utilization, thread utilization, and shader activity.

公开(公告)号：US11113784B2

公开(公告)日：2021-09-07

申请号：US17064427

申请日：2020-10-06

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Scott Janus ,  Varghese George ,  Subramaniam Maiyuran ,  Altug Koker ,  Abhishek Appu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Andrei Valentin ,  Ashutosh Garg ,  Yoav Harel ,  Arthur Hunter, Jr. ,  SungYe Kim ,  Mike Macpherson ,  Elmoustapha Ould-Ahmed-Vall ,  William Sadler ,  Lakshminarayanan Striramassarma ,  Vikranth Vemulapalli

IPC: G06T1/20 ,  G06F9/50 ,  G06F15/80 ,  G06F12/0806 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06F7/544

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

公开(公告)号：US20210256654A1

公开(公告)日：2021-08-19

申请号：US17161941

申请日：2021-01-29

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Josh Mastronarde ,  Naveen Matam ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

公开(公告)号：US11016929B2

公开(公告)日：2021-05-25

申请号：US16354782

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Aravindh Anantaraman ,  Abhishek R. Appu ,  Altug Koker ,  Elmoustapha Ould-Ahmed-Vall ,  Valentin Andrei ,  Subramaniam Maiyuran ,  Nicolas Galappo Von Borries ,  Varghese George ,  Mike Macpherson ,  Ben Ashbaugh ,  Murali Ramadoss ,  Vikranth Vemulapalli ,  William Sadler ,  Jonathan Pearce ,  Sungye Kim

IPC: G06T1/00 ,  G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.