公开(公告)号：US20200006510A1

公开(公告)日：2020-01-02

申请号：US16490866

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Sean T. Ma ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Harold W. Kennel ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/04 ,  H01L29/66

Abstract: In various embodiments, the disclosure describes transistors having non-vertical gates. In one embodiment, the non-vertical gates can have a curved or wide angle gate in order to reduce the electric field crowing on the drain side of the gate edge and/or portions having corners and thereby reduce leakage current in the transistor. In one embodiment, the non-vertical gate can be generated by one or more etching steps (for example, isotropic etching steps) of an underlying channel during the fabrication of a transistor having the non-vertical gate. In one embodiment, the non-vertical gate can be generated by one or more directional etching steps that may expose various facets having predetermined orientations of a source and/or drain associated with the transistor.

公开(公告)号：US10461193B2

公开(公告)日：2019-10-29

申请号：US15575322

申请日：2015-05-27

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Gilbert Dewey ,  Anand S. Murthy ,  Glenn A. Glass ,  Willy Rachmady ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz

IPC: H01L29/00 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

Abstract: Transistor devices may be formed having a buffer between an active channel and a substrate, wherein the active channel and a portion of the buffer form a gated region. The active channel may comprise a low band-gap material on a sub-structure, e.g. the buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electron mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure.

公开(公告)号：US20190273133A1

公开(公告)日：2019-09-05

申请号：US16347110

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Glenn A. Glass ,  Van H. Le ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Willy Rachmady

IPC: H01L29/08 ,  H01L29/165 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L29/45 ,  H01L29/417 ,  H01L29/10

Abstract: Disclosed herein are transistor amorphous interlayer arrangements, and related methods and devices. For example, in some embodiments, transistor amorphous interlayer arrangement may include a channel material and a transistor source/drain stack. The transistor source/drain stack may include a transistor electrode material configured to be a transistor source/drain contact, i.e. either a source contact or a drain contact of the transistor, and a doped amorphous semiconductor material disposed between the transistor electrode material and the channel material.

公开(公告)号：US10388733B2

公开(公告)日：2019-08-20

申请号：US16248708

申请日：2019-01-15

Applicant: Intel Corporation

Inventor： Van H. Le ,  Benjamin Chu-Kung ,  Harold Hal W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/161 ,  H01L29/15 ,  H01L29/165 ,  H01L29/10 ,  H01L21/283 ,  H01L21/02 ,  H01L29/786

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

公开(公告)号：US10347767B2

公开(公告)日：2019-07-09

申请号：US15570742

申请日：2015-06-16

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Ashish Agrawal

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

Abstract: A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing sidewalls. The fin comprises a first semiconductor material. The subfin layer comprises a III-V semiconductor material.

公开(公告)号：US10340374B2

公开(公告)日：2019-07-02

申请号：US15755450

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Sean T. Ma ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/775 ,  H01L29/201 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/06

Abstract: Monolithic FETs including a channel region of a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering the channel region, an impurity-doped compositionally graded semiconductor is grown, for example on at least a drain end of the channel region to introduce a carrier-blocking conduction band offset and/or a wider band gap within the drain region of the transistor. In some embodiments, the compositional grade induces a carrier-blocking band offset of at least 0.25 eV. The wider band gap and/or band offset contributes to a reduced gate induced drain leakage (GIDL). The impurity-doped semiconductor may be compositionally graded back down from the retrograded composition to a suitably narrow band gap material providing good ohmic contact. In some embodiments, the impurity-doped compositionally graded semiconductor growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.

公开(公告)号：US20190189753A1

公开(公告)日：2019-06-20

申请号：US16326663

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Matthew Metz ,  Gilbert Dewey ,  Harold W. Kennel ,  Cheng-Ying Huang ,  Sean T. Ma ,  Willy Rachmady

IPC: H01L29/12 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L29/122 ,  H01L21/02543 ,  H01L21/02546 ,  H01L29/20

Abstract: Semiconductor devices, computing devices, and related methods are disclosed herein. A semiconductor device includes a seed material, an epitaxial material in contact with the seed material, and at least one quantum region including an elastic stiffness that is greater than an elastic stiffness of the epitaxial material. The epitaxial material has lattice parameters that are different from lattice parameters of the seed material by at least a threshold amount. Lattice parameters of the quantum region are within the threshold amount of the lattice parameters of the epitaxial material. A method includes disposing an epitaxial material on a seed material, disposing a quantum region on the epitaxial material, and disposing the epitaxial material on the quantum region.

公开(公告)号：US10249490B2

公开(公告)日：2019-04-02

申请号：US15458897

申请日：2017-03-14

Applicant: Intel Corporation

Inventor： Niti Goel ,  Robert S. Chau ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Niloy Mukherjee ,  Nancy M. Zelick ,  Gilbert Dewey ,  Willy Rachmady ,  Marko Radosavljevic ,  Van H. Le ,  Ravi Pillarisetty ,  Sansaptak Dasgupta

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/205 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

公开(公告)号：US20190043974A1

公开(公告)日：2019-02-07

申请号：US15900655

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  James S. Clarke ,  Willy Rachmady

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.

公开(公告)号：US10103263B2

公开(公告)日：2018-10-16

申请号：US15609755

申请日：2017-05-31

Applicant: Intel Corporation

Inventor： Van H. Le ,  Harold W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack Kavalieros ,  Niloy Mukherjee

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/20 ,  H01L29/775 ,  B82Y99/00

Abstract: Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.