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公开(公告)号：US06258659B1
公开(公告)日：2001-07-10
申请号：US09725412
申请日：2000-11-29
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/10864 , H01L27/10885 , H01L27/10891
摘要： A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports.
摘要翻译： 一种用于生产非常高密度嵌入式DRAM /非常高性能逻辑结构的方法，包括在支撑体中制造具有水银源/漏极和栅极导体双功函数MOSFET的垂直MOSFET DRAM单元。
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52.发明授权公开(公告)号：US07439128B2
公开(公告)日：2008-10-21
申请号：US11124324
申请日：2005-05-06
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864
摘要： The present invention comprises a method including the steps of providing a substrate; forming a trench in the substrate; forming a buried plate in the substrate about the trench; depositing a dielectric layer within the trench; and then depositing a P-type metal atop the dielectric layer, where the dielectric layer is positioned between the P-type metal and the buried plate. Another aspect of the present invention provides a trench capacitor where said trench capacitor comprises a trench formed in a substrate, a buried plate formed in the substrate about the trench; a node dielectric; and a P-type metal liner deposited within the trench, where the P-type metal liner is separated from the buried plate by the node dielectric. A P-type metal is defined as a metal having a work function close to the Si valence band, approximately equal to 5.1 eV.
摘要翻译： 本发明包括一种方法，包括提供基底的步骤; 在基板中形成沟槽; 在沟槽周围形成衬底; 在沟槽内沉积介电层; 然后在电介质层的顶部沉积P型金属，其中电介质层位于P型金属和掩埋板之间。 本发明的另一方面提供一种沟槽电容器，其中所述沟槽电容器包括形成在衬底中的沟槽，在衬底周围形成的掩埋板围绕沟槽; 节点电介质; 以及沉积在沟槽内的P型金属衬垫，其中P型金属衬垫通过节点电介质与掩埋板分离。 P型金属被定义为具有接近于Si价带的功函数的金属，大约等于5.1eV。
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公开(公告)号：US06818528B2
公开(公告)日：2004-11-16
申请号：US10004152
申请日：2001-10-24
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/308
摘要： A method for forming multi-depth apertures in a substrate is provided. The method includes first providing a pad stack atop a surface of a substrate having regions for forming apertures therein, the pad stack includes at least a top patterned masking layer. Next, at least one of the regions of the substrate is blocked with a first block mask, while leaving at least one other region of the substrate unblocked. A plurality of first apertures having a first depth is then formed in the unblocked region of the substrate using the patterned masking layer to define the plurality of first apertures. The first block mask is then removed; and thereafter a plurality of second apertures having a second depth is formed in regions of the substrate that were previously blocked by the first block mask using the same patterned masking layer to define the second apertures, while simultaneously increasing the first depth such that the first depth is deeper than the second depth.
摘要翻译： 提供了一种在衬底中形成多深度孔的方法。 该方法包括首先在具有用于在其中形成孔的区域的基底的表面顶部提供衬垫叠层，所述衬垫堆叠至少包括顶部图案化掩模层。 接下来，衬底的至少一个区域用第一块掩模阻挡，同时留下衬底的至少一个其它区域被阻挡。 然后使用图案化的掩模层在衬底的未阻挡区域中形成具有第一深度的多个第一孔，以限定多个第一孔。 然后删除第一个块掩码; 此后，在衬底的预先被第一块掩模阻挡的区域中形成具有第二深度的多个第二孔，使用相同的图案化掩模层来限定第二孔，同时增加第一深度使得第一深度 比第二深度更深。
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54.发明授权Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect 有权具有硅化位线和多晶硅互连的嵌入式垂直DRAM阵列公开(公告)号：US06727539B2
公开(公告)日：2004-04-27
申请号：US10147150
申请日：2002-05-16
IPC分类号： H01L27108
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/10876 , H01L27/10894
摘要： A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.
摘要翻译： 用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域中制造具有硅化多晶硅层的垂直MOSFET DRAM单元，着陆焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠。 该工艺消除了对M0金属化层的需要。
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公开(公告)号：US06727141B1
公开(公告)日：2004-04-27
申请号：US10342419
申请日：2003-01-14
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10864 , H01L27/10876
摘要： The distance between buried straps in a DRAM array of trench capacitor/vertical transistor cells is increased by offsetting adjacent cells by a vertical offset distance, so that the total distance between adjacent straps is increased without increasing the horizontal distance between cells.
摘要翻译： 沟槽电容器/垂直晶体管单元的DRAM阵列中的埋地带之间的距离通过将相邻单元偏移垂直偏移距离而增加，使得相邻带之间的总距离增加而不增加单元之间的水平距离。
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56.发明授权公开(公告)号：US06703274B1
公开(公告)日：2004-03-09
申请号：US10336988
申请日：2003-01-03
IPC分类号： H02L218242
CPC分类号： H01L27/10867 , H01L27/10864 , H01L27/10876
摘要： A DRAM cell with a vertical transistor forms a buried strap outdiffusion with reduced lateral extent by shifting high temperature steps that affect the thermal budget before the initial buried strap diffusion. The gate conductor is formed in two steps, with poly sidewalls being put down above a sacrificial Trench top oxide to form a self-aligned poly-gate insulator structure before the formation of the LDD extension.
摘要翻译： 具有垂直晶体管的DRAM单元通过在初始掩埋带扩散之前移动影响热预算的高温步骤而形成具有减小的横向扩展的埋地带外扩散。 栅极导体形成为两个阶段，其中多个侧壁被放置在牺牲沟槽顶部氧化物之上，以在形成LDD延伸之前形成自对准多晶硅绝缘体结构。
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公开(公告)号：US06590259B2
公开(公告)日：2003-07-08
申请号：US10000198
申请日：2001-11-02
IPC分类号： H01L2701
CPC分类号： H01L27/10864 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.
摘要翻译： 提出了一种半导体器件，其涉及一种形成嵌入式DRAM和逻辑器件的方法，其中DRAM器件以块状形成，单晶半导体区域和逻辑器件形成在绝缘体上硅（“SOI”）区域中， 其中掩埋的掺杂玻璃用作掩模以形成用于存储在本体区域中的深沟槽。 还公开了所得到的结构。
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公开(公告)号：US06504210B1
公开(公告)日：2003-01-07
申请号：US09599484
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jeffrey Peter Gambino , Jack A. Mandelman , Viraj Sardesai , Mary Elizabeth Weybright
发明人： Ramachandra Divakaruni , Jeffrey Peter Gambino , Jack A. Mandelman , Viraj Sardesai , Mary Elizabeth Weybright
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/28044 , H01L27/10873 , H01L27/10876 , H01L27/10891 , H01L29/4941 , H01L29/6653 , H01L29/66553
摘要： A fully polysilicon encapsulated metal-containing damascene gate structure is provided that is useful in Gigabit DRAM (dynamic random access memory) device. The fully encapsulated metal-containing damascene gate comprises a semiconductor substrate having a gate oxide layer formed on a surface portion of said substrate; a gate polysilicon layer formed on said gate oxide layer; a metal layer formed on said polysilicon layer; and a cap oxide layer formed on said metal layer, wherein said metal layer is completely encapsulated by said polysilicon and oxide layers. The damascene gate structure may also include polysilicon spacers formed on said gate polysilicon layer and said metal layer is encapsulated therein and outer polysilicon sidewalls that are oxidized.
摘要翻译： 提供了一种完全多晶硅封装的含金属镶嵌栅极结构，可用于千兆DRAM（动态随机存取存储器）器件。 完全封装的含金属的镶嵌栅极包括具有形成在所述基板的表面部分上的栅极氧化层的半导体基板; 形成在所述栅极氧化物层上的栅极多晶硅层; 形成在所述多晶硅层上的金属层; 以及形成在所述金属层上的帽氧化层，其中所述金属层被所述多晶硅和氧化物层完全包封。 镶嵌栅极结构还可以包括形成在所述栅极多晶硅层上的多晶硅间隔物，并且所述金属层被封装在其中，并且外部多晶硅侧壁被氧化。
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公开(公告)号：US06420750B1
公开(公告)日：2002-07-16
申请号：US09635203
申请日：2000-08-09
IPC分类号： H01L27108
CPC分类号： H01L27/10867
摘要： A method and structure for forming an integrated circuit memory device includes forming a trench conductor in a trench, forming an isolation collar along a perimeter of an upper portion of the trench conductor, forming supporting spacers above the isolation collar, forming a sacrificial layer between the supporting spacers along an upper surface of the trench conductor, forming an insulator above the sacrificial layer, forming a gate conductor above the insulator, removing the sacrificial layer to form a gap between the insulator and the trench conductor, wherein the supporting spacers maintain a relative position of the gate conductor, the insulator and the trench conductor and forming a conductive strap in the gap.
摘要翻译： 用于形成集成电路存储器件的方法和结构包括在沟槽中形成沟槽导体，沿着沟槽导体的上部的周边形成隔离环，在隔离套环的上方形成支撑隔板，在隔离环之间形成牺牲层 沿着沟槽导体的上表面支撑间隔物，在牺牲层之上形成绝缘体，在绝缘体上方形成栅极导体，去除牺牲层以在绝缘体和沟槽导体之间形成间隙，其中支撑间隔件保持相对 栅极导体，绝缘体和沟槽导体的位置，并在间隙中形成导电带。
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60.发明授权公开(公告)号：US06281064B1
公开(公告)日：2001-08-28
申请号：US09325941
申请日：1999-06-04
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L27/10873 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A method for providing dual work function doping and borderless array diffusion contacts includes providing a semiconductor substrate, a gate insulator, a conductor on the gate insulator, an insulating cap on the conductor and insulating spacers on sidewalls of a portion of the conductor and the insulating cap. The method also includes doping portions of the semiconductor substrate and the conductor with a first conductive type and other portions with a second conductive type. The conductor may be annealed such that dopants of the first and second conductive types spread over the respective conductors.
摘要翻译： 一种用于提供双工作功能掺杂和无边界阵列扩散接触的方法包括提供半导体衬底，栅极绝缘体，栅极绝缘体上的导体，导体上的绝缘帽和导体的一部分的侧壁上的绝缘衬垫和绝缘 帽。 该方法还包括以第一导电类型和具有第二导电类型的其它部分掺杂半导体衬底和导体的部分。 导体可以退火，使得第一和第二导电类型的掺杂物分布在相应的导体上。
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