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    Directionally etched nanowire field effect transistors
    53.
    发明授权
    Directionally etched nanowire field effect transistors 失效
    定向蚀刻纳米线场效应晶体管

    公开(公告)号：US08361907B2

    公开(公告)日：2013-01-29

    申请号：US12776485

    申请日：2010-05-10

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Jeffrey W. Sleight

    IPC分类号： H01L29/72

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/84 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

    摘要： A method for forming a nanowire field effect transistor (FET) device includes depositing a first semiconductor layer on a substrate wherein a surface of the semiconductor layer is parallel to {110} crystalline planes of the semiconductor layer, epitaxially depositing a second semiconductor layer on the first semiconductor layer, etching the first semiconductor layer and the second semiconductor layer to define a nanowire channel portion that connects a source region pad to a drain region pad, the nanowire channel portion having sidewalls that are parallel to {100} crystalline planes, and the source region pad and the drain region pad having sidewalls that are parallel to {110} crystalline planes, and performing an anisotropic etch that removes primarily material from {100} crystalline planes of the first semiconductor layer such that the nanowire channel portion is suspended by the source region pad and the drain region pad.

    摘要翻译： 一种形成纳米线场效应晶体管（FET）器件的方法包括在衬底上沉积第一半导体层，其中半导体层的表面平行于半导体层的{110}晶面，在其上外延地沉积第二半导体层 第一半导体层，蚀刻第一半导体层和第二半导体层以限定将源极区焊盘连接到漏极区焊盘的纳米线沟道部分，纳米线沟道部分具有​​平行于{100}晶面的侧壁，并且 源极区焊盘和漏极区焊盘具有平行于{110}晶面的侧壁，并且执行各向异性蚀刻，主要从第一半导体层的{100}晶面去除材料，使得纳米线通道部分被 源区焊盘和漏极区焊盘。

    DIRECTIONALLY ETCHED NANOWIRE FIELD EFFECT TRANSISTORS
    56.
    发明申请
    DIRECTIONALLY ETCHED NANOWIRE FIELD EFFECT TRANSISTORS 有权
    方向蚀刻的纳米效应晶体管

    公开(公告)号：US20120280204A1

    公开(公告)日：2012-11-08

    申请号：US13550700

    申请日：2012-07-17

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Jeffrey W. Sleight

    IPC分类号： H01L29/08

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/84 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

    摘要： A nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes.

    摘要翻译： 一种纳米线场效应晶体管（FET）器件，包括源极区域，该源极区域包括设置在第二半导体层上的第一半导体层，源区域具有平行于{110}晶面的表面和与{110}晶体平行的相对侧壁表面 平面，包括设置在第二半导体层上的第一半导体层的漏极区域，源极区域具有平行于{110}晶面的面和平行于{110}晶面的相对侧壁表面，并且纳米线通道构件悬挂 源极区和漏极区，其中纳米线通道包括第一半导体层，平行于{100}晶面的相对侧壁表面和平行于{110}晶面的相对面。

    Omega shaped nanowire tunnel field effect transistors fabrication
    57.
    发明授权
    Omega shaped nanowire tunnel field effect transistors fabrication 有权
    欧米茄形纳米线隧道场效应晶体管制造

    公开(公告)号：US08143113B2

    公开(公告)日：2012-03-27

    申请号：US12630939

    申请日：2009-12-04

    申请人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC分类号： H01L21/00

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/26586 ,  H01L21/31111 ,  H01L21/31155 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

    摘要： A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.

    摘要翻译： 一种形成纳米线隧道场效应晶体管器件的方法包括形成连接到第一焊盘区域和第二焊盘区域的纳米线，纳米线包括芯部分和电介质层，在纳米线的电介质层上形成栅极结构， 在所述纳米线的部分上形成第一保护隔离物，在所述暴露的纳米线和所述第一焊盘区域的第一部分中注入离子，将所述暴露的纳米线和所述第二焊盘区域的第二部分的电介质层注入， 从所述第二焊盘区域和所述第二部分去除所述暴露的纳米线的第二部分的芯部分以形成空腔，以及在所述空腔中外延生长掺杂半导体材料，以将所述纳米线的暴露的横截面与所述第二焊盘 地区。

    Nanowire Field Effect Transistors
    58.
    发明申请
    Nanowire Field Effect Transistors 有权
    纳米线场效应晶体管

    公开(公告)号：US20120068150A1

    公开(公告)日：2012-03-22

    申请号：US12884707

    申请日：2010-09-17

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L29/775 ,  H01L21/336 ,  H01L29/772

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/84 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/78696

    摘要： A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer.

    摘要翻译： 一种用于形成纳米线场效应晶体管（FET）器件的方法，包括形成绝缘体上硅（SOI）焊盘区域，第二SOI焊盘区域，第三SOI焊盘区域，将第一SOI焊盘区域连接到第一SOI焊盘区域的第一SOI部分 第二SOI焊盘区域和将第二SOI焊盘区域连接到衬底上的第三SOI焊盘区域的第二SOI部分，在第二SOI部分上形成第一硬掩模层，在半导体衬底上形成第一悬浮的纳米线，形成第一 围绕第一悬浮纳米线的一部分构造栅极结构，在第一栅极结构和第一悬置纳米线上图案化第二硬掩模层，去除第一硬掩模层，在半导体衬底上形成第二悬浮纳米线，在第二栅极结构周围形成第二栅极结构 第二悬浮纳米线的一部分，以及去除第二硬掩模层。

    PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS
    60.
    发明申请
    PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS 失效
    平面和纳米级场效应晶体管

    公开(公告)号：US20110133167A1

    公开(公告)日：2011-06-09

    申请号：US12631342

    申请日：2009-12-04

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L29/66 ,  H01L21/336 ,  H01L29/786

    CPC分类号： H01L29/78696 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66772

    摘要： A method for forming an integrated circuit, the method includes forming a first nanowire suspended above an insulator substrate, the first nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region that are disposed on the insulator substrate, a second nanowire disposed on the insulator substrate attached to a third SOI pad region and a fourth SOI pad region that are disposed on the insulator substrate, and a SOI slab region that is disposed on the insulator substrate, and forming a first gate surrounding a portion of the first nanowire, a second gate on a portion of the second nanowire, and a third gate on a portion of the SOI slab region.

    摘要翻译： 一种用于形成集成电路的方法，所述方法包括形成悬置在绝缘体衬底上的第一纳米线，所述第一纳米线附接到绝缘体上的第一绝缘体（SOI）焊盘区域和设置在所述绝缘体衬底上的第二SOI焊盘区域， 布置在绝缘体基板上的第二纳米线，其连接到设置在绝缘体基板上的第三SOI焊盘区域和第四SOI焊盘区域，以及SOI板状区域，其设置在绝缘体基板上，并且形成围绕部分的第一栅极 的第一纳米线，第二纳米线的一部分上的第二栅极和SOI板区域的一部分上的第三栅极。